MMC_CAP_SD_HIGHSPEED | MMC_CAP_8_BIT_DATA |\
MMC_CAP_SDIO_IRQ)
-static struct dw_mci_board pci_board_data = {
- .caps = DW_MCI_CAPABILITIES,
+static const struct dw_mci_drv_data pci_drv_data = {
+ .common_caps = DW_MCI_CAPABILITIES,
};
static int dw_mci_pci_probe(struct pci_dev *pdev,
host->irq = pdev->irq;
host->irq_flags = IRQF_SHARED;
- host->pdata = &pci_board_data;
host->fifo_depth = 32;
host->detect_delay_ms = 200;
host->bus_hz = 33 * 1000 * 1000;
+ host->drv_data = &pci_drv_data;
ret = pcim_iomap_regions(pdev, 1 << PCI_BAR_NO, pci_name(pdev));
if (ret)
struct mmc_host *mmc = host->mmc;
int ctrl_id;
- if (host->pdata->caps)
- mmc->caps = host->pdata->caps;
-
if (drv_data)
mmc->caps |= drv_data->common_caps;
spin_unlock_irqrestore(&host->irq_lock, irqflags);
}
-#ifdef CONFIG_OF
-static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
+static int dw_mci_parse_dt(struct dw_mci *host)
{
- struct dw_mci_board *pdata;
struct device *dev = host->dev;
const struct dw_mci_drv_data *drv_data = host->drv_data;
int ret;
u32 clock_frequency;
- pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
- if (!pdata)
- return ERR_PTR(-ENOMEM);
-
/* find reset controller when exist */
host->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
if (IS_ERR(host->rstc))
- return ERR_CAST(host->rstc);
+ return PTR_ERR(host->rstc);
- if (device_property_read_u32(dev, "fifo-depth", &host->fifo_depth))
+ if (!host->fifo_depth && device_property_read_u32(dev, "fifo-depth", &host->fifo_depth))
dev_info(dev,
"fifo-depth property not found, using value of FIFOTH register as default\n");
- device_property_read_u32(dev, "card-detect-delay",
- &host->detect_delay_ms);
+ if (!host->detect_delay_ms)
+ device_property_read_u32(dev, "card-detect-delay",
+ &host->detect_delay_ms);
- device_property_read_u32(dev, "data-addr", &host->data_addr_override);
+ if (!host->data_addr_override)
+ device_property_read_u32(dev, "data-addr", &host->data_addr_override);
if (device_property_present(dev, "fifo-watermark-aligned"))
host->wm_aligned = true;
- if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
+ if (!host->bus_hz && !device_property_read_u32(dev, "clock-frequency", &clock_frequency))
host->bus_hz = clock_frequency;
if (drv_data && drv_data->parse_dt) {
ret = drv_data->parse_dt(host);
if (ret)
- return ERR_PTR(ret);
+ return ret;
}
- return pdata;
-}
-
-#else /* CONFIG_OF */
-static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
-{
- return ERR_PTR(-EINVAL);
+ return 0;
}
-#endif /* CONFIG_OF */
static void dw_mci_enable_cd(struct dw_mci *host)
{
int width, i, ret = 0;
u32 fifo_size;
- if (!host->pdata) {
- host->pdata = dw_mci_parse_dt(host);
- if (IS_ERR(host->pdata))
- return dev_err_probe(host->dev, PTR_ERR(host->pdata),
- "platform data not available\n");
- }
+ ret = dw_mci_parse_dt(host);
+ if (ret)
+ return dev_err_probe(host->dev, ret, "parse dt failed\n");
host->biu_clk = devm_clk_get(host->dev, "biu");
if (IS_ERR(host->biu_clk)) {
* @fifoth_val: The value of FIFOTH register.
* @verid: Denote Version ID.
* @dev: Device associated with the MMC controller.
- * @pdata: Platform data associated with the MMC controller.
* @drv_data: Driver specific data for identified variant of the controller
* @priv: Implementation defined private data.
* @biu_clk: Pointer to bus interface unit clock instance.
u32 fifoth_val;
u16 verid;
struct device *dev;
- struct dw_mci_board *pdata;
const struct dw_mci_drv_data *drv_data;
void *priv;
struct clk *biu_clk;
void (*exit)(struct dw_mci *host);
};
-/* Board platform data */
-struct dw_mci_board {
- u32 caps; /* Capabilities */
-};
-
/* Support for longer data read timeout */
#define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0)
/* Force 32-bit access to the FIFO */