pru: Add options to disable MUL/FILL/ZERO instructions

Older PRU core versions (e.g. in AM1808 SoC) do not support
XIN, XOUT, FILL, ZERO instructions.  Add GCC command line options to
optionally disable generation of those instructions, so that code
can be executed on such older PRU cores.

gcc/ChangeLog:

	* common/config/pru/pru-common.cc (TARGET_DEFAULT_TARGET_FLAGS):
	Keep multiplication, FILL and ZERO instructions enabled by
	default.
	* config/pru/pru.md (prumov<mode>): Gate code generation on
	TARGET_OPT_FILLZERO.
	(mov<mode>): Ditto.
	(zero_extendqidi2): Ditto.
	(zero_extendhidi2): Ditto.
	(zero_extendsidi2): Ditto.
	(@pru_ior_fillbytes<mode>): Ditto.
	(@pru_and_zerobytes<mode>): Ditto.
	(@<code>di3): Ditto.
	(mulsi3): Gate code generation on TARGET_OPT_MUL.
	* config/pru/pru.opt: Add mmul and mfillzero options.
	* config/pru/pru.opt.urls: Regenerate.
	* config/rl78/rl78.opt.urls: Regenerate.
	* doc/invoke.texi: Document new options.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>

diff --git a/gcc/common/config/pru/pru-common.cc b/gcc/common/config/pru/pru-common.cc
index dcc27b913d409b361df8281f3c444fa63bff644a..19e35702530b97e7be3832c7d53485a55182e68a 100644 (file)
--- a/gcc/common/config/pru/pru-common.cc
+++ b/gcc/common/config/pru/pru-common.cc
@@ -28,7 +28,8 @@ along with GCC; see the file COPYING3.  If not see
 #include "flags.h"
 
 #undef TARGET_DEFAULT_TARGET_FLAGS
-#define TARGET_DEFAULT_TARGET_FLAGS            (MASK_OPT_LOOP)
+#define TARGET_DEFAULT_TARGET_FLAGS \
+  (MASK_OPT_LOOP | MASK_OPT_MUL | MASK_OPT_FILLZERO)
 
 #undef TARGET_EXCEPT_UNWIND_INFO
 #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info

diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 3504e42e9002e78127811230c5843d3900f84ca5..b8ef55b98f93c56ae77f66e104c1e8a96c8700f1 100644 (file)
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -215,7 +215,7 @@
     mov\\t%0, %1
     ldi\\t%0, %%pmem(%1)
     ldi\\t%0, %1
-    fill\\t%0, 4
+    * return TARGET_OPT_FILLZERO ? \"fill\\t%0, 4\" : \"ldi32\\t%0, 0xffffffff\";
     ldi32\\t%0, %1"
   [(set_attr "type" "st,ld,alu,alu,alu,alu,alu")
    (set_attr "length" "4,4,4,4,4,4,8")])
@@ -259,9 +259,11 @@
     case 1:
       return "lb%B1o\\t%b0, %1, %S1";
     case 2:
-      return "zero\\t%F0, 8";
+      return TARGET_OPT_FILLZERO ? "zero\\t%F0, 8"
+                                : "ldi\\t%F0, 0\;ldi\\t%N0, 0";
     case 3:
-      return "fill\\t%F0, 8";
+      return TARGET_OPT_FILLZERO ? "fill\\t%F0, 8"
+                                : "ldi32\\t%F0, 0xffffffff\;mov\\t%N0, %F0";
     case 4:
       /* careful with overlapping source and destination regs.  */
       gcc_assert (GP_REG_P (REGNO (operands[0])));
@@ -502,7 +504,7 @@
 (define_insn "zero_extendqidi2"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
        (zero_extend:DI (match_operand:QI 1 "register_operand" "0,r")))]
-  ""
+  "TARGET_OPT_FILLZERO"
   "@
     zero\\t%F0.b1, 7
     mov\\t%F0.b0, %1\;zero\\t%F0.b1, 7"
@@ -512,7 +514,7 @@
 (define_insn "zero_extendhidi2"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
        (zero_extend:DI (match_operand:HI 1 "register_operand" "0,r")))]
-  ""
+  "TARGET_OPT_FILLZERO"
   "@
     zero\\t%F0.b2, 6
     mov\\t%F0.w0, %1\;zero\\t%F0.b2, 6"
@@ -522,7 +524,7 @@
 (define_insn "zero_extendsidi2"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
        (zero_extend:DI (match_operand:SI 1 "register_operand" "0,r")))]
-  ""
+  "TARGET_OPT_FILLZERO"
   "@
     zero\\t%N0, 4
     mov\\t%F0, %1\;zero\\t%N0, 4"
@@ -535,7 +537,7 @@
 (define_expand "extend<EQS0:mode><EQDHIDI:mode>2"
   [(set (match_operand:EQDHIDI 0 "register_operand" "=r")
        (sign_extend:EQDHIDI (match_operand:EQS0 1 "register_operand" "r")))]
-  ""
+  "TARGET_OPT_FILLZERO"
 {
   rtx_code_label *skip_hiset_label;
 
@@ -744,7 +746,7 @@
        (ior:HIDI
           (match_operand:HIDI 1 "register_operand" "0")
           (match_operand:HIDI 2 "const_fillbytes_operand" "Uf")))]
-  ""
+  "TARGET_OPT_FILLZERO"
 {
   static char line[64];
   pru_byterange r;
@@ -767,7 +769,7 @@
        (and:HIDI
           (match_operand:HIDI 1 "register_operand" "0")
           (match_operand:HIDI 2 "const_zerobytes_operand" "Uz")))]
-  ""
+  "TARGET_OPT_FILLZERO"
 {
   static char line[64];
   pru_byterange r;
@@ -1114,7 +1116,8 @@
   /* Try with the more efficient zero/fill patterns first.  */
   if (<LOGICAL_BITOP:CODE> == IOR
       && CONST_INT_P (operands[2])
-      && const_fillbytes_operand (operands[2], DImode))
+      && const_fillbytes_operand (operands[2], DImode)
+      && TARGET_OPT_FILLZERO)
     {
       rtx insn = maybe_gen_pru_ior_fillbytes (DImode,
                                              operands[0],
@@ -1130,7 +1133,8 @@
     }
   if (<LOGICAL_BITOP:CODE> == AND
       && CONST_INT_P (operands[2])
-      && const_zerobytes_operand (operands[2], DImode))
+      && const_zerobytes_operand (operands[2], DImode)
+      && TARGET_OPT_FILLZERO)
     {
       rtx insn = maybe_gen_pru_and_zerobytes (DImode,
                                              operands[0],
@@ -1212,7 +1216,7 @@
   [(set (match_operand:SI 0 "pru_muldst_operand"          "=Rmd0")
        (mult:SI (match_operand:SI 1 "pru_mulsrc0_operand" "%Rms0")
                 (match_operand:SI 2 "pru_mulsrc1_operand" "Rms1")))]
-  ""
+  "TARGET_OPT_MUL"
   "nop\;xin\\t0, %0, 4"
   [(set_attr "type" "alu")
    (set_attr "length" "8")])

diff --git a/gcc/config/pru/pru.opt b/gcc/config/pru/pru.opt
index 8385beba567e1d5a24be62fe90563bdb64f811d9..5206b2aec820ae9e58ded7f864f7a55fc45e2a07 100644 (file)
--- a/gcc/config/pru/pru.opt
+++ b/gcc/config/pru/pru.opt
@@ -39,6 +39,14 @@ mloop
 Target Mask(OPT_LOOP)
 Allow (or do not allow) gcc to use the LOOP instruction.
 
+mmul
+Target Mask(OPT_MUL)
+Allow (or do not allow) gcc to use the PRU multiplier unit.
+
+mfillzero
+Target Mask(OPT_FILLZERO)
+Allow (or do not allow) gcc to use the FILL and ZERO instructions.
+
 mabi=
 Target RejectNegative Joined Enum(pru_abi_t) Var(pru_current_abi) Init(PRU_ABI_GNU) Save
 Select target ABI variant.

diff --git a/gcc/config/pru/pru.opt.urls b/gcc/config/pru/pru.opt.urls
index c87affb112b87374a44c977c96c597b60e63e809..5c5789214bd5423b1ff7284914e59545af5ae652 100644 (file)
--- a/gcc/config/pru/pru.opt.urls
+++ b/gcc/config/pru/pru.opt.urls
@@ -12,6 +12,12 @@ UrlSuffix(gcc/PRU-Options.html#index-mno-relax-1)
 mloop
 UrlSuffix(gcc/PRU-Options.html#index-mloop)
 
+mmul
+UrlSuffix(gcc/PRU-Options.html#index-mmul)
+
+mfillzero
+UrlSuffix(gcc/PRU-Options.html#index-mfillzero)
+
 mabi=
 UrlSuffix(gcc/PRU-Options.html#index-mabi-4)
 

diff --git a/gcc/config/rl78/rl78.opt.urls b/gcc/config/rl78/rl78.opt.urls
index 96eff5f720410ea5277020fbf864f82e608b48a4..66e874be589b76183c4065ef0edcfe9159359203 100644 (file)
--- a/gcc/config/rl78/rl78.opt.urls
+++ b/gcc/config/rl78/rl78.opt.urls
@@ -4,7 +4,7 @@ msim
 UrlSuffix(gcc/RL78-Options.html#index-msim-6)
 
 mmul=
-UrlSuffix(gcc/RL78-Options.html#index-mmul)
+UrlSuffix(gcc/RL78-Options.html#index-mmul-1)
 
 mallregs
 UrlSuffix(gcc/RL78-Options.html#index-mallregs)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 931e8aaa62323b3328597a467fe9a80dd4122b07..56c4fa86e346676557774e83a782bff994758a6f 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1265,7 +1265,7 @@ See RS/6000 and PowerPC Options.
 
 @emph{PRU Options} (@ref{PRU Options})
 @gccoptlist{-mmcu=@var{mcu}  -minrt  -mno-relax  -mloop
--mabi=@var{variant}}
+-mmul -mfillzero -mabi=@var{variant}}
 
 @emph{RISC-V Options} (@ref{RISC-V Options})
 @gccoptlist{-mbranch-cost=@var{N-instruction}
@@ -31322,6 +31322,14 @@ instead of the @option{--relax} option.
 @item -mloop
 Allow (or do not allow) GCC to use the LOOP instruction.
 
+@opindex mmul
+@item -mmul
+Allow (or do not allow) GCC to use the PRU multiplier unit.
+
+@opindex mfillzero
+@item -mfillzero
+Allow (or do not allow) GCC to use the FILL and ZERO instructions.
+
 @opindex mabi
 @item -mabi=@var{variant}
 Specify the ABI variant to output code for.  @option{-mabi=ti} selects the