+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Add FORM.
+ * testsuite/gas/aarch64/morello_insn-c64.d: Add tests.
+ * testsuite/gas/aarch64/morello_insn.d: Likewise.
+ * testsuite/gas/aarch64/morello_insn.s: Likewise.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands): Add IMM6_EXT.
po_misc_or_fail (parse_perms (&str, info));
break;
+ case AARCH64_OPND_FORM:
+ {
+ char *start = str;
+ do
+ str++;
+ while (ISALPHA (*str));
+ info->form = get_form_from_str (start, str - start);
+ if (info->form == NULL)
+ {
+ set_syntax_error (_("invalid form"));
+ goto failure;
+ }
+ }
+ break;
+
case AARCH64_OPND_COND:
case AARCH64_OPND_COND1:
{
.*: c2d07bff scbnds csp, csp, #0x20, lsl #4
.*: c2dffbff scbnds csp, csp, #0x3f, lsl #4
.*: c2c27bff scbnds csp, csp, #0x4, lsl #4
+.*: c2c33062 seal c2, c3, rb
+.*: c2c37062 seal c2, c3, lb
+.*: c2c35062 seal c2, c3, lpb
.*: c2d928c7 bicflgs c7, c6, x25
.*: c2d9a8c7 eorflgs c7, c6, x25
.*: c2d968c7 orrflgs c7, c6, x25
.*: c2c4c440 rets c29, c2, c4
.*: c2cd2482 cpytype c2, c4, c13
.*: c2cd6482 cpyvalue c2, c4, c13
+.*: c2cd0882 seal c2, c4, c13
+.*: c2cd4882 unseal c2, c4, c13
.*: c2d9eac0 cthi c0, c22, x25
.*: c2d9e89f cthi csp, c4, x25
.*: c2f91816 cvt c22, c0, x25
.*: c2d07bff scbnds csp, csp, #0x20, lsl #4
.*: c2dffbff scbnds csp, csp, #0x3f, lsl #4
.*: c2c27bff scbnds csp, csp, #0x4, lsl #4
+.*: c2c33062 seal c2, c3, rb
+.*: c2c37062 seal c2, c3, lb
+.*: c2c35062 seal c2, c3, lpb
.*: c2d928c7 bicflgs c7, c6, x25
.*: c2d9a8c7 eorflgs c7, c6, x25
.*: c2d968c7 orrflgs c7, c6, x25
.*: c2c4c440 rets c29, c2, c4
.*: c2cd2482 cpytype c2, c4, c13
.*: c2cd6482 cpyvalue c2, c4, c13
+.*: c2cd0882 seal c2, c4, c13
+.*: c2cd4882 unseal c2, c4, c13
.*: c2d9eac0 cthi c0, c22, x25
.*: c2d9e89f cthi csp, c4, x25
.*: c2f91816 cvt c22, c0, x25
morello_scbnds c18, csp
morello_scbnds csp, csp
+ .macro morello_seal cd, cn
+ .irp form, rb, lb, lpb
+ seal \cd, \cn, \form
+ .endr
+ .endm
+morello_seal c2, c3
+
// Three operands (dnm)
.macro morello_cspcspx cdsp, cnsp, xm
morello_jump_sealed c2, c4
.macro morello_ccc cd, cn, cm
- .irp op, cpytype, cpyvalue
+ .irp op, cpytype, cpyvalue, seal, unseal
\op \cd, \cn, \cm
.endr
.endm
+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * config/aarch64.h (aarch64_operand_class): Add FORM.
+ (aarch64_opnd): Likewise.
+ (aarch64_form): New struct.
+ (aarch64_forms): New array.
+ (get_form_from_value, get_form_from_str): New functions.
+ (aarch64_opnd_info): New member FORM.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* include/aarch64.h (aarch64_opnd): Add IMM6_EXT.
AARCH64_OPND_CLASS_COND,
AARCH64_OPND_CLASS_CAP_REG,
AARCH64_OPND_CLASS_PERM,
+ AARCH64_OPND_CLASS_FORM,
};
/* Operand code that helps both parsing and coding.
AARCH64_OPND_A64C_IMM8, /* IMM8 for BICFLGS. */
AARCH64_OPND_A64C_IMM6_EXT, /* IMM6 for SCBNDS. */
AARCH64_OPND_PERM, /* 3-bit capability permission for e.g. CLRPERM. */
+ AARCH64_OPND_FORM, /* 2-bit capability form for e.g. SEAL. */
};
/* Qualifier constrains an operand. It either specifies a variant of an
/* Capability permissions. */
aarch64_insn get_perm_bit (const char p);
+
+typedef struct
+{
+ const char *name;
+ aarch64_insn value;
+} aarch64_form;
+
+extern const aarch64_form aarch64_forms[4];
+
+const aarch64_form *get_form_from_value (aarch64_insn value);
+const aarch64_form *get_form_from_str (const char *form, size_t len);
\f
/* Structure representing an operand. */
const aarch64_cond *cond;
aarch64_insn perm;
+ const aarch64_form *form;
/* The encoding of the PSTATE field. */
aarch64_insn pstatefield;
const aarch64_sys_ins_reg *sysins_op;
+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_form): New function.
+ * aarch64-asm.h (ins_form): New function declaration.
+ * aarch64-dis.c (aarch64_ext_form): New function.
+ * aarch64-dis.h (ext_form): New function declaraion.
+ * aarch64-opc.c (fields): New field form.
+ (aarch64_forms): Initialise array.
+ (get_form_from_value, get_form_from_str): New functions.
+ (aarch64_print_operand): Add FORM.
+ * aarch64-opc.h (aarch64_field_kind): Add FLD_form.
+ * aarch64-tbl.h (aarch64_opcode_table): New instructions.
+ (AARCH64_OPERANDS): New operands.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_ins_aimm): Fix comment.
return true;
}
+/* Encode the form operand for e.g. SEAL <Cd>, <Cn>, <form>. */
+bool
+aarch64_ins_form (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ /* form */
+ insert_field (FLD_form, code, info->form->value, 0);
+ return true;
+}
+
/* Encode the system register operand for e.g. MRS <Xt>, <systemreg>. */
bool
aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
AARCH64_DECL_OPD_INSERTER (ins_simd_addr_post);
AARCH64_DECL_OPD_INSERTER (ins_cond);
AARCH64_DECL_OPD_INSERTER (ins_perm);
+AARCH64_DECL_OPD_INSERTER (ins_form);
AARCH64_DECL_OPD_INSERTER (ins_sysreg);
AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
return true;
}
+/* Decode the form operand for e.g. SEAL <Cd>, <Cn>, <form>. */
+bool
+aarch64_ext_form (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ aarch64_insn value;
+ /* form */
+ value = extract_field (FLD_form, code, 0);
+ info->form = get_form_from_value (value);
+ return true;
+}
+
/* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
bool
aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
AARCH64_DECL_OPD_EXTRACTOR (ext_simd_addr_post);
AARCH64_DECL_OPD_EXTRACTOR (ext_cond);
AARCH64_DECL_OPD_EXTRACTOR (ext_perm);
+AARCH64_DECL_OPD_EXTRACTOR (ext_form);
AARCH64_DECL_OPD_EXTRACTOR (ext_sysreg);
AARCH64_DECL_OPD_EXTRACTOR (ext_pstatefield);
AARCH64_DECL_OPD_EXTRACTOR (ext_sysins_op);
{ 13, 8 }, /* a64c_imm8: BICFLGS imm8. */
{ 14, 1 }, /* a64c_shift: Shift bit in SCBNDS. */
{ 13, 3 }, /* perm: permission specifier in clrperm. */
+ { 13, 2 }, /* form: form specifier in seal. */
};
enum aarch64_operand_class
return 8;
}
+/* Table of all forms. */
+const aarch64_form aarch64_forms[] =
+{
+ {NULL, 0x0}, /* RESERVED */
+ {"rb", 0x1},
+ {"lpb", 0x2},
+ {"lb", 0x3},
+};
+
+const aarch64_form *
+get_form_from_value (aarch64_insn value)
+{
+ assert (value < sizeof (aarch64_forms) / sizeof (aarch64_form));
+ return &aarch64_forms[(unsigned int) value];
+}
+
+const aarch64_form *
+get_form_from_str (const char *form, size_t len)
+{
+ for (unsigned i = 1; i < sizeof (aarch64_forms) / sizeof (aarch64_form); i++)
+ if (!strncmp (form, aarch64_forms[i].name, len))
+ return &aarch64_forms[i];
+
+ return NULL;
+}
+
/* Table describing the operand extension/shifting operators; indexed by
enum aarch64_modifier_kind.
}
break;
+ case AARCH64_OPND_FORM:
+ snprintf (buf, size, "%s", opnd->form->name);
+ break;
+
case AARCH64_OPND_COND:
case AARCH64_OPND_COND1:
snprintf (buf, size, "%s", opnd->cond->names[0]);
FLD_a64c_imm8,
FLD_a64c_shift,
FLD_perm,
+ FLD_form,
};
/* Field description. */
A64C_INSN ("scoff", 0xc2c06000, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0),
A64C_INSN ("sctag", 0xc2c08000, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0),
A64C_INSN ("scvalue", 0xc2c04000, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0),
+ A64C_INSN ("seal", 0xc2c00800, 0xffe0fc00, a64c, 0, OP3 (Cad, Can, Cam), QL3_A64C_CA_CA_CA, 0),
+ A64C_INSN ("seal", 0xc2c31000, 0xffff9c00, a64c, 0, OP3 (Cad, Can, FORM), QL3_A64C_CA_CA_NIL, 0),
+ A64C_INSN ("unseal", 0xc2c04800, 0xffe0fc00, a64c, 0, OP3 (Cad, Can, Cam), QL3_A64C_CA_CA_CA, 0),
/* TME Instructions. */
_TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
_TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0),
X(IMMEDIATE, ins_aimm, ext_a64c_imm6, "A64C_IMM6_EXT", 0, \
F(FLD_a64c_shift, FLD_imm6_2), \
"6-bit unsigned immediate") \
- Y(PERM, perm, "PERM", 0, F(), "a capability permission")
+ Y(PERM, perm, "PERM", 0, F(), "a capability permission") \
+ Y(FORM, form, "FORM", 0, F(), "a capability form")
projects / thirdparty / binutils-gdb.git / commitdiff
