Tighten up an instruction decoding exception for

add.w reg, sp, #constT.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2173

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index 5fdd1dd679edd03af30105c62d51ca4b0aa4e58b..d9a3797bf262782de9dd664d40d1f271ae6edd9d 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -16019,7 +16019,7 @@ DisResult disInstr_THUMB_WRK (
       UInt rD = INSN1(11,8);
       Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
       /* but allow "add.w reg, sp, #constT" */ 
-      if (!valid && rN == 13)
+      if (!valid && rN == 13 && rD != 15)
          valid = True;
       if (valid) {
          IRTemp argL  = newTemp(Ity_I32);