ARM: dts: aspeed: anacapa: Add JTAG CPLD TRST pin to SGPIO map

Add JTAG_CPLD_TRST_R_N to the sgpiom0 pin name table on Facebook Anacapa
BMC. This exposes the CPLD JTAG TRST signal through SGPIO, allowing
proper JTAG reset control during debug.

[arj: Minor tidying of commit message formatting]

Signed-off-by: Colin Huang <u8813345@gmail.com>
Link: https://patch.msgid.link/20260511-add-jtag-trst-pin-v1-1-b0be2f7b2da5@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
index 2cb7bd128d24e73d512d8d6a7b6a35c28c891767..9a43e0c87257ced8a29950785e05b01f03fea483 100644 (file)
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
@@ -882,7 +882,7 @@
        /* C0-C7 line 32-47 */
        "RSVD_RMC_GPIO3", "", "", "",
        "", "", "", "",
-       "LEAK_DETECT_RMC_N", "", "", "",
+       "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "",
        "", "", "", "",
 
        /* D0-D7 line 48-63 */