]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: lx2160a: change i2c0 (iic1) pinmux mask to one bit
authorJosua Mayer <josua@solid-run.com>
Tue, 24 Mar 2026 12:40:56 +0000 (13:40 +0100)
committerFrank Li <Frank.Li@nxp.com>
Fri, 27 Mar 2026 13:53:26 +0000 (09:53 -0400)
LX2160A pinmux is done in groups by various length bitfields within
configuration registers.

The first i2c bus (called IIC1 in reference manual) is configured through
field IIC1_PMUX in register RCWSR14 bit 10 which is described in the
reference manual as a single bit, unlike the other i2c buses.

Change the bitmask for the pinmux nodes from 0x7 to 0x1 to ensure only
single bit is modified.

Further change the zero in the same line to hexadecimal format for
consistency.

Align with documentation by avoiding writes to reserved bits. No functional
change, as writing the extra two reserved bits is not known to cause
issues.

Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

index af74e77efabc55c4ffe24d33e1fdd1b75cc8e9e8..d5bb55df03216d1ddc45e092d8b43609f8984acd 100644 (file)
                        };
 
                        i2c0_scl: i2c0-scl-pins {
-                               pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
+                               pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
                        };
 
                        i2c0_scl_gpio: i2c0-scl-gpio-pins {
-                               pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
+                               pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>;
                        };
                };