re PR target/14209 (Bug in cris.md, shrinking access size of postincrement.)

	PR target/14209
	* config/cris/cris.md ("*andsi_movu", "*andhi_movu"): Tweak
	constraints to not match postincrement.  Adjust the predicate to
	exclude a volatile memory reference.
	("*andsi_clear"): Tweak constraints to not match postincrement.
	Adjust the predicate to exclude a volatile memory reference.
	("*andhi_clear"): Ditto.  Rename from "*andhi_clear_signed".
	("*andhi_clear_unsigned"): Remove, non-matching pattern.

From-SVN: r78256

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 254e5440f5a3fb5fbbbba7030578b380adffb3c8..d4458e93c4b7d533b017e8f64564065625d99637 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2004-02-22  Hans-Peter Nilsson  <hp@axis.com>
+
+       PR target/14209
+       * config/cris/cris.md ("*andsi_movu", "*andhi_movu"): Tweak
+       constraints to not match postincrement.  Adjust the predicate to
+       exclude a volatile memory reference.
+       ("*andsi_clear"): Tweak constraints to not match postincrement.
+       Adjust the predicate to exclude a volatile memory reference.
+       ("*andhi_clear"): Ditto.  Rename from "*andhi_clear_signed".
+       ("*andhi_clear_unsigned"): Remove, non-matching pattern.
+
 2004-02-14  Release Manager
 
        * GCC 3.3.3 Released.

diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 25d196f4f68fab7779024eb65a7f509676dcb0be..b98115db70ad04121cfbbab4ffbdcfee472792fc 100644 (file)
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -2682,17 +2682,19 @@
 
 (define_insn "*andsi_movu"
   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-       (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q>,m")
+       (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To")
                (match_operand:SI 2 "const_int_operand" "n,n,n")))]
-  "INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535"
+  "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535)
+   && (GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1]))"
   "movu.%z2 %1,%0"
   [(set_attr "slottable" "yes,yes,no")])
 
 (define_insn "*andsi_clear"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q>,Q>,m,m")
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To")
        (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
                (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))]
-  "INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256"
+  "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256)
+   && (GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0]))"
   "@
    cLear.b %0
    cLear.w %0
@@ -2770,27 +2772,17 @@
 
 (define_insn "*andhi_movu"
   [(set (match_operand:HI 0 "register_operand" "=r,r,r")
-       (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q>,m")
+       (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To")
                (const_int 255)))]
-  ""
+  "GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1])"
   "mOvu.b %1,%0"
   [(set_attr "slottable" "yes,yes,no")])
 
-(define_insn "*andhi_clear_signed"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q>,m")
+(define_insn "*andhi_clear"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To")
        (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
                (const_int -256)))]
-  ""
-  "cLear.b %0"
-  [(set_attr "slottable" "yes,yes,no")
-   (set_attr "cc" "none")])
-
-;; FIXME: Either this or the pattern above should be redundant.
-(define_insn "*andhi_clear_unsigned"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q>,m")
-       (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
-               (const_int 65280)))]
-  ""
+  "GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])"
   "cLear.b %0"
   [(set_attr "slottable" "yes,yes,no")
    (set_attr "cc" "none")])