},
.uhr_cap = {
.has_uhr = true,
- .phy.cap = IEEE80211_UHR_PHY_CAP_ELR_RX |
- IEEE80211_UHR_PHY_CAP_ELR_TX,
+ /* Note: asymmetry is fixed later */
+ .phy.cap = cpu_to_le32(IEEE80211_UHR_PHY_CAP_ELR_RX |
+ IEEE80211_UHR_PHY_CAP_ELR_TX),
.mac.mac_cap = {
[0] = IEEE80211_UHR_MAC_CAP0_NPCA_SUPP |
IEEE80211_UHR_MAC_CAP0_DPS_SUPP,
},
.uhr_cap = {
.has_uhr = true,
- .phy.cap = IEEE80211_UHR_PHY_CAP_ELR_RX |
- IEEE80211_UHR_PHY_CAP_ELR_TX,
+ /* Note: asymmetry is fixed later */
+ .phy.cap = cpu_to_le32(IEEE80211_UHR_PHY_CAP_ELR_RX |
+ IEEE80211_UHR_PHY_CAP_ELR_TX),
},
},
};
}
if (uhr_cap && uhr_cap->has_uhr && own_uhr_cap &&
- uhr_cap->phy.cap & IEEE80211_UHR_PHY_CAP_ELR_RX &&
- own_uhr_cap->phy.cap & IEEE80211_UHR_PHY_CAP_ELR_TX)
+ uhr_cap->phy.cap & cpu_to_le32(IEEE80211_UHR_PHY_CAP_ELR_RX) &&
+ own_uhr_cap->phy.cap & cpu_to_le32(IEEE80211_UHR_PHY_CAP_ELR_TX))
flags |= IWL_TLC_MNG_CFG_FLAGS_UHR_ELR_1_5_MBPS_MSK |
IWL_TLC_MNG_CFG_FLAGS_UHR_ELR_3_MBPS_MSK;
.mac.mac_cap = {
[0] = IEEE80211_UHR_MAC_CAP0_NPCA_SUPP,
},
- .phy.cap = IEEE80211_UHR_PHY_CAP_ELR_RX |
- IEEE80211_UHR_PHY_CAP_ELR_TX,
+ .phy.cap = cpu_to_le32(IEEE80211_UHR_PHY_CAP_ELR_RX |
+ IEEE80211_UHR_PHY_CAP_ELR_TX),
},
},
{
.mac.mac_cap = {
[0] = IEEE80211_UHR_MAC_CAP0_NPCA_SUPP,
},
- .phy.cap = IEEE80211_UHR_PHY_CAP_ELR_RX |
- IEEE80211_UHR_PHY_CAP_ELR_TX,
+ .phy.cap = cpu_to_le32(IEEE80211_UHR_PHY_CAP_ELR_RX |
+ IEEE80211_UHR_PHY_CAP_ELR_TX),
},
},
#ifdef CONFIG_MAC80211_MESH
.mac.mac_cap = {
[0] = IEEE80211_UHR_MAC_CAP0_NPCA_SUPP,
},
- .phy.cap = IEEE80211_UHR_PHY_CAP_ELR_RX |
- IEEE80211_UHR_PHY_CAP_ELR_TX,
+ .phy.cap = cpu_to_le32(IEEE80211_UHR_PHY_CAP_ELR_TX),
},
},
{
.mac.mac_cap = {
[0] = IEEE80211_UHR_MAC_CAP0_NPCA_SUPP,
},
- .phy.cap = IEEE80211_UHR_PHY_CAP_ELR_RX |
- IEEE80211_UHR_PHY_CAP_ELR_TX,
+ .phy.cap = cpu_to_le32(IEEE80211_UHR_PHY_CAP_ELR_RX),
},
},
#ifdef CONFIG_MAC80211_MESH
.mac.mac_cap = {
[0] = IEEE80211_UHR_MAC_CAP0_NPCA_SUPP,
},
- .phy.cap = IEEE80211_UHR_PHY_CAP_ELR_RX |
- IEEE80211_UHR_PHY_CAP_ELR_TX,
+ .phy.cap = cpu_to_le32(IEEE80211_UHR_PHY_CAP_ELR_TX),
},
},
{
.mac.mac_cap = {
[0] = IEEE80211_UHR_MAC_CAP0_NPCA_SUPP,
},
- .phy.cap = IEEE80211_UHR_PHY_CAP_ELR_RX |
- IEEE80211_UHR_PHY_CAP_ELR_TX,
+ .phy.cap = cpu_to_le32(IEEE80211_UHR_PHY_CAP_ELR_RX),
},
},
#ifdef CONFIG_MAC80211_MESH
.mac.mac_cap = {
[0] = IEEE80211_UHR_MAC_CAP0_NPCA_SUPP,
},
- .phy.cap = IEEE80211_UHR_PHY_CAP_ELR_RX |
- IEEE80211_UHR_PHY_CAP_ELR_TX,
+ .phy.cap = cpu_to_le32(IEEE80211_UHR_PHY_CAP_ELR_RX |
+ IEEE80211_UHR_PHY_CAP_ELR_TX),
},
},
#endif
u8 mac_cap[5];
} __packed;
-#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_SND_NDP_LE80 0x01
-#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_DL_MU_LE80 0x02
-#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_SND_NDP_160 0x04
-#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_DL_MU_160 0x08
-#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_SND_NDP_320 0x10
-#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_DL_MU_320 0x20
-#define IEEE80211_UHR_PHY_CAP_ELR_RX 0x40
-#define IEEE80211_UHR_PHY_CAP_ELR_TX 0x80
+#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_SND_NDP_LE80 0x00000001
+#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_DL_MU_LE80 0x00000002
+#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_SND_NDP_160 0x00000004
+#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_DL_MU_160 0x00000008
+#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_SND_NDP_320 0x00000010
+#define IEEE80211_UHR_PHY_CAP_MAX_NSS_RX_DL_MU_320 0x00000020
+#define IEEE80211_UHR_PHY_CAP_ELR_TX 0x00000040
+#define IEEE80211_UHR_PHY_CAP_ELR_RX 0x00000080
+#define IEEE80211_UHR_PHY_CAP_PART_BW_DL_MUMIMO 0x00000100
+#define IEEE80211_UHR_PHY_CAP_PART_BW_UL_MUMIMO 0x00000200
+#define IEEE80211_UHR_PHY_CAP_MCS15 0x00000400
+#define IEEE80211_UHR_PHY_CAP_2XLDPC_TX 0x00000800
+#define IEEE80211_UHR_PHY_CAP_2XLDPC_RX 0x00001000
+#define IEEE80211_UHR_PHY_CAP_UEQM_TX_MAX_NSS 0x00006000
+#define IEEE80211_UHR_PHY_CAP_UEQM_RX_MAX_NSS 0x00018000
+#define IEEE80211_UHR_PHY_CAP_CO_BF_JOINT_SOUNDING 0x00040000
+#define IEEE80211_UHR_PHY_CAP_IM_TX 0x00080000
+#define IEEE80211_UHR_PHY_CAP_IM_RX 0x00100000
+#define IEEE80211_UHR_PHY_CAP_CO_SR_MODE_1 0x00200000
+#define IEEE80211_UHR_PHY_CAP_CO_SR_MODE_2 0x00400000
+#define IEEE80211_UHR_PHY_CAP_DRU_DBW_20_IN_PBW_20 0x00800000
+#define IEEE80211_UHR_PHY_CAP_DRU_DBW_40_IN_PBW_40 0x01000000
+#define IEEE80211_UHR_PHY_CAP_DRU_DBW_80_IN_PBW_80 0x02000000
+#define IEEE80211_UHR_PHY_CAP_DRU_DBW_80_IN_PBW_160 0x04000000
+#define IEEE80211_UHR_PHY_CAP_DRU_DBW_80_IN_PBW_320 0x08000000
+#define IEEE80211_UHR_PHY_CAP_DRU_DBW_20_IN_PBW_GE80 0x10000000
+#define IEEE80211_UHR_PHY_CAP_DRU_DBW_40_IN_PBW_GE80 0x20000000
+#define IEEE80211_UHR_PHY_CAP_DRU_DBW_60_IN_PBW_GE80 0x40000000
+#define IEEE80211_UHR_PHY_CAP_DRU_RRU_HYBRID_MODE 0x80000000
struct ieee80211_uhr_cap_phy {
- u8 cap;
+ __le32 cap;
+ u8 reserved;
} __packed;
struct ieee80211_uhr_cap {