install.texi: Change ` bit' to `-bit'.

	* doc/install.texi: Change ` bit' to `-bit'.
	* doc/md.texi: Change `-bits' to `-bit'.
	* doc/tm.texi: Change `-bits' to ` bits'.

From-SVN: r55034

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8b91b1bb32780b13bbd4bc646f1b74964527aebb..4dda2ebc29cd9a4e3874dc3eb77e05aa4c759bd4 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2002-06-27  Matt Kraai  <kraai@alumni.cmu.edu>
+
+       * doc/install.texi: Change ` bit' to `-bit'.
+       * doc/md.texi: Change `-bits' to `-bit'.
+       * doc/tm.texi: Change `-bits' to ` bits'.
+       
 2002-06-24  David S. Miller  <davem@redhat.com>
 
        * config/sparc/sparc.h (INIT_TARGET_OPTABS): If ARCH64, set the

diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 8a40c47e76e7f40ba4c73b4be912d40905b61565..d20a9264339b66e5de5ea42ab040f490da18b2fd 100644 (file)
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -3230,7 +3230,7 @@ its maximum of 262144 bytes.  If you have root access, you can use the
 GCC does not correctly pass/return structures which are
 smaller than 16 bytes and which are not 8 bytes.  The problem is very
 involved and difficult to fix.  It affects a number of other targets also,
-but IRIX 6 is affected the most, because it is a 64 bit target, and 4 byte
+but IRIX 6 is affected the most, because it is a 64-bit target, and 4 byte
 structures are common.  The exact problem is that structures are being padded
 at the wrong end, e.g.@: a 4 byte structure is loaded into the lower 4 bytes
 of the register when it should be loaded into the upper 4 bytes of the
@@ -3446,7 +3446,7 @@ S/390 system running Linux for S/390@.
 <hr>
 @end html
 @heading @anchor{s390x-*-linux*}s390x-*-linux*
-zSeries system (64 Bit) running Linux for zSeries@.
+zSeries system (64-bit) running Linux for zSeries@.
 
 @html
 </p>
@@ -3766,7 +3766,7 @@ respects, this target is the same as the
 </p>
 <hr>
 @end html
-@heading @anchor{windows}Microsoft Windows (32 bit)
+@heading @anchor{windows}Microsoft Windows (32-bit)
 
 A port of GCC 2.95.x is included with the
 @uref{http://www.cygwin.com/,,Cygwin environment}.

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 652198df4eb8cdcb8dab988af13eb4efb58a39b6..b38ef5ee54a778ff647f105b10614c4ca71b01fd 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -1869,7 +1869,7 @@ A constant in the range supported by @code{movrcc} instructions
 
 @item N
 Same as @samp{K}, except that it verifies that bits that are not in the
-lower 32-bits range are all zero.  Must be used instead of @samp{K} for
+lower 32-bit range are all zero.  Must be used instead of @samp{K} for
 modes wider than @code{SImode}
 
 @item G

diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 3d9e453ef63bdd14c993672cd407d56890ea319c..e98ed3fd9b3c0204d5eb4c33501ac081d42f4643 100644 (file)
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -2454,14 +2454,14 @@ A C expression that is true if, for a register in
 @code{CLASS_CANNOT_CHANGE_MODE}, the requested mode punning is invalid.
 
 For the example, loading 32-bit integer or floating-point objects into
-floating-point registers on the Alpha extends them to 64-bits.
+floating-point registers on the Alpha extends them to 64 bits.
 Therefore loading a 64-bit object and then storing it as a 32-bit object
-does not store the low-order 32-bits, as would be the case for a normal
+does not store the low-order 32 bits, as would be the case for a normal
 register.  Therefore, @file{alpha.h} defines @code{CLASS_CANNOT_CHANGE_MODE}
 as @code{FLOAT_REGS} and @code{CLASS_CANNOT_CHANGE_MODE_P} restricts
 mode changes to same-size modes.
 
-Compare this to IA-64, which extends floating-point values to 82-bits,
+Compare this to IA-64, which extends floating-point values to 82 bits,
 and stores 64-bit integers in a different format than 64-bit doubles.
 Therefore @code{CLASS_CANNOT_CHANGE_MODE_P} is always true.
 @end table