]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
dt-bindings: clock: Add RaspberryPi RP1 clock bindings
authorAndrea della Porta <andrea.porta@suse.com>
Thu, 29 May 2025 13:50:38 +0000 (15:50 +0200)
committerFlorian Fainelli <florian.fainelli@broadcom.com>
Mon, 9 Jun 2025 17:10:30 +0000 (10:10 -0700)
Add device tree bindings for the clock generator found in RP1 multi
function device, and relative entries in MAINTAINERS file.

Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/20250529135052.28398-1-andrea.porta@suse.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml [new file with mode: 0644]
include/dt-bindings/clock/raspberrypi,rp1-clocks.h [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml b/Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml
new file mode 100644 (file)
index 0000000..cc4491f
--- /dev/null
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/raspberrypi,rp1-clocks.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RaspberryPi RP1 clock generator
+
+maintainers:
+  - A. della Porta <andrea.porta@suse.com>
+
+description: |
+  The RP1 contains a clock generator designed as three PLLs (CORE, AUDIO,
+  VIDEO), and each PLL output can be programmed through dividers to generate
+  the clocks to drive the sub-peripherals embedded inside the chipset.
+
+  Link to datasheet:
+  https://datasheets.raspberrypi.com/rp1/rp1-peripherals.pdf
+
+properties:
+  compatible:
+    const: raspberrypi,rp1-clocks
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+    description:
+      The available clocks are defined in
+      include/dt-bindings/clock/raspberrypi,rp1-clocks.h.
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/raspberrypi,rp1-clocks.h>
+
+    rp1 {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        clocks@c040018000 {
+            compatible = "raspberrypi,rp1-clocks";
+            reg = <0xc0 0x40018000 0x0 0x10038>;
+            #clock-cells = <1>;
+            clocks = <&clk_rp1_xosc>;
+        };
+    };
diff --git a/include/dt-bindings/clock/raspberrypi,rp1-clocks.h b/include/dt-bindings/clock/raspberrypi,rp1-clocks.h
new file mode 100644 (file)
index 0000000..248efb8
--- /dev/null
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2021 Raspberry Pi Ltd.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
+#define __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
+
+#define RP1_PLL_SYS_CORE               0
+#define RP1_PLL_AUDIO_CORE             1
+#define RP1_PLL_VIDEO_CORE             2
+
+#define RP1_PLL_SYS                    3
+#define RP1_PLL_AUDIO                  4
+#define RP1_PLL_VIDEO                  5
+
+#define RP1_PLL_SYS_PRI_PH             6
+#define RP1_PLL_SYS_SEC_PH             7
+#define RP1_PLL_AUDIO_PRI_PH           8
+
+#define RP1_PLL_SYS_SEC                        9
+#define RP1_PLL_AUDIO_SEC              10
+#define RP1_PLL_VIDEO_SEC              11
+
+#define RP1_CLK_SYS                    12
+#define RP1_CLK_SLOW_SYS               13
+#define RP1_CLK_DMA                    14
+#define RP1_CLK_UART                   15
+#define RP1_CLK_ETH                    16
+#define RP1_CLK_PWM0                   17
+#define RP1_CLK_PWM1                   18
+#define RP1_CLK_AUDIO_IN               19
+#define RP1_CLK_AUDIO_OUT              20
+#define RP1_CLK_I2S                    21
+#define RP1_CLK_MIPI0_CFG              22
+#define RP1_CLK_MIPI1_CFG              23
+#define RP1_CLK_PCIE_AUX               24
+#define RP1_CLK_USBH0_MICROFRAME       25
+#define RP1_CLK_USBH1_MICROFRAME       26
+#define RP1_CLK_USBH0_SUSPEND          27
+#define RP1_CLK_USBH1_SUSPEND          28
+#define RP1_CLK_ETH_TSU                        29
+#define RP1_CLK_ADC                    30
+#define RP1_CLK_SDIO_TIMER             31
+#define RP1_CLK_SDIO_ALT_SRC           32
+#define RP1_CLK_GP0                    33
+#define RP1_CLK_GP1                    34
+#define RP1_CLK_GP2                    35
+#define RP1_CLK_GP3                    36
+#define RP1_CLK_GP4                    37
+#define RP1_CLK_GP5                    38
+#define RP1_CLK_VEC                    39
+#define RP1_CLK_DPI                    40
+#define RP1_CLK_MIPI0_DPI              41
+#define RP1_CLK_MIPI1_DPI              42
+
+/* Extra PLL output channels - RP1B0 only */
+#define RP1_PLL_VIDEO_PRI_PH           43
+#define RP1_PLL_AUDIO_TERN             44
+
+#endif