};
static const struct regmap_irq max77759_chgr_irqs[] = {
- REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0,
- MAX77759_CHGR_REG_CHG_INT_AICL),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0,
- MAX77759_CHGR_REG_CHG_INT_CHGIN),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0,
- MAX77759_CHGR_REG_CHG_INT_WCIN),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0,
- MAX77759_CHGR_REG_CHG_INT_CHG),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0,
- MAX77759_CHGR_REG_CHG_INT_BAT),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0,
- MAX77759_CHGR_REG_CHG_INT_INLIM),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0,
- MAX77759_CHGR_REG_CHG_INT_THM2),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0,
- MAX77759_CHGR_REG_CHG_INT_BYP),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1,
- MAX77759_CHGR_REG_CHG_INT2_INSEL),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1,
- MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1,
- MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1,
- MAX77759_CHGR_REG_CHG_INT2_BAT_OILO),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1,
- MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1,
- MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1,
- MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO),
- REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1,
- MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0, MAX77759_CHGR_REG_CHG_INT_AICL),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0, MAX77759_CHGR_REG_CHG_INT_CHGIN),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0, MAX77759_CHGR_REG_CHG_INT_WCIN),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0, MAX77759_CHGR_REG_CHG_INT_CHG),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0, MAX77759_CHGR_REG_CHG_INT_BAT),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0, MAX77759_CHGR_REG_CHG_INT_INLIM),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0, MAX77759_CHGR_REG_CHG_INT_THM2),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0, MAX77759_CHGR_REG_CHG_INT_BYP),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1, MAX77759_CHGR_REG_CHG_INT2_INSEL),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1, MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1, MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1, MAX77759_CHGR_REG_CHG_INT2_BAT_OILO),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO),
+ REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE),
};
static const struct regmap_irq_chip max77759_pmic_irq_chip = {