drm/amd/pm: Change get_enabled_mask signature

Use smu_feature_bits instead of uint64_t pointer and operate on
feature bits.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 75897ac203c32751a7420e8d812d1d99faa5af8a..797da21e2e5f679ea2598e8856dd7bb46d0f1518 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1646,7 +1646,7 @@ static int smu_smc_hw_setup(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        uint8_t pcie_gen = 0, pcie_width = 0;
-       uint64_t features_supported;
+       struct smu_feature_bits features_supported;
        int ret = 0;
 
        switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
@@ -1807,7 +1807,7 @@ static int smu_smc_hw_setup(struct smu_context *smu)
                return ret;
        }
        smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED,
-                                 (unsigned long *)&features_supported);
+                            features_supported.bits);
 
        if (!smu_is_dpm_running(smu))
                dev_info(adev->dev, "dpm has been disabled\n");
@@ -3152,10 +3152,19 @@ static int smu_read_sensor(void *handle,
                *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100;
                *size = 4;
                break;
-       case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
-               ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
+       case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: {
+               struct smu_feature_bits feature_mask;
+               uint32_t features[2];
+
+               /* TBD: need to handle for > 64 bits */
+               ret = smu_feature_get_enabled_mask(smu, &feature_mask);
+               if (!ret) {
+                       smu_feature_bits_to_arr32(&feature_mask, features, 64);
+                       *(uint64_t *)data = *(uint64_t *)features;
+               }
                *size = 8;
                break;
+       }
        case AMDGPU_PP_SENSOR_UVD_POWER:
                *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
                *size = 4;

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index c58290686f0d01de0661a83f1582bef4a79d017d..4019ef8595040330d5c92789562841817c7f2cb3 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1229,7 +1229,8 @@ struct pptable_funcs {
         *                    on the SMU.
         * &feature_mask: Enabled feature mask.
         */
-       int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);
+       int (*get_enabled_mask)(struct smu_context *smu,
+                               struct smu_feature_bits *feature_mask);
 
        /**
         * @feature_is_enabled: Test if a feature is enabled.
@@ -2061,6 +2062,12 @@ static inline bool smu_feature_bits_empty(const struct smu_feature_bits *bits,
        return bitmap_empty(bits->bits, nbits);
 }
 
+static inline bool smu_feature_bits_full(const struct smu_feature_bits *bits,
+                                        unsigned int nbits)
+{
+       return bitmap_full(bits->bits, nbits);
+}
+
 static inline void smu_feature_bits_copy(struct smu_feature_bits *dst,
                                         const unsigned long *src,
                                         unsigned int nbits)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 814f24b7ccc4cb8547f3b8886788345e3820a612..0c4afd1e1aab0d5330895ac5275668cec22b5d3f 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -1527,15 +1527,14 @@ static int arcturus_set_performance_level(struct smu_context *smu,
 static bool arcturus_is_dpm_running(struct smu_context *smu)
 {
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&arcturus_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         arcturus_dpm_features.bits);
 }
 
 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index 406acfbbbc63a9d9094b46e397fc79cf94d234ef..87953a4d0a4339e27b17b72f5e5c02857fd7357b 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -363,8 +363,7 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        /* we need to re-init after suspend so return false */
        if (adev->in_suspend)
@@ -381,8 +380,8 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu)
                cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK,
                        &cyan_skillfish_sclk_default);
 
-       smu_feature_bits_to_arr32(&cyan_skillfish_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         cyan_skillfish_dpm_features.bits);
 }
 
 static ssize_t cyan_skillfish_get_gpu_metrics(struct smu_context *smu,
@@ -569,12 +568,13 @@ static int cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu,
        return 0;
 }
 
-static int cyan_skillfish_get_enabled_mask(struct smu_context *smu,
-                                          uint64_t *feature_mask)
+static int
+cyan_skillfish_get_enabled_mask(struct smu_context *smu,
+                               struct smu_feature_bits *feature_mask)
 {
        if (!feature_mask)
                return -EINVAL;
-       memset(feature_mask, 0xff, sizeof(*feature_mask));
+       smu_feature_bits_fill(feature_mask);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index f5be643951084f99852d6cbe44098f77ba205d61..737bfdfb814c587f28d2c94fcc329abef6c23723 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1621,15 +1621,14 @@ static int navi10_display_config_changed(struct smu_context *smu)
 static bool navi10_is_dpm_running(struct smu_context *smu)
 {
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&navi10_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         navi10_dpm_features.bits);
 }
 
 static int navi10_get_fan_speed_rpm(struct smu_context *smu,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 7d23b6c8c5388768a5994ff9bf34d0cfd3f2faf7..6268bc5ed3e68fbd9f83dff74aa35a705c47ef92 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1536,15 +1536,14 @@ static int sienna_cichlid_display_config_changed(struct smu_context *smu)
 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
 {
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&sienna_cichlid_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         sienna_cichlid_dpm_features.bits);
 }
 
 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index f8b76577d008722cc8bb020a66080a7c82582f16..08179840697e10ebe7a647e9a03d2ad090d77e77 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -506,8 +506,7 @@ static bool vangogh_is_dpm_running(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        /* we need to re-init after suspend so return false */
        if (adev->in_suspend)
@@ -518,8 +517,8 @@ static bool vangogh_is_dpm_running(struct smu_context *smu)
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&vangogh_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         vangogh_dpm_features.bits);
 }
 
 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 5346b60b09b980c8b8a675139b4ad76bc336138b..31e21ff8859a54a1bdfb39213efbc726ea542b58 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -1434,11 +1434,11 @@ static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
 }
 
 static int renoir_get_enabled_mask(struct smu_context *smu,
-                                  uint64_t *feature_mask)
+                                  struct smu_feature_bits *feature_mask)
 {
        if (!feature_mask)
                return -EINVAL;
-       memset(feature_mask, 0xff, sizeof(*feature_mask));
+       smu_feature_bits_fill(feature_mask);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 4185c7282a11f126fe8622039f0d7e57d5029d89..ad23682217eeb59c59d33b3d732993d93b7c0dac 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -1398,14 +1398,13 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_
 static bool aldebaran_is_dpm_running(struct smu_context *smu)
 {
        int ret;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
        if (ret)
                return false;
-       smu_feature_bits_to_arr32(&aldebaran_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         aldebaran_dpm_features.bits);
 }
 
 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 0856c1c34d7a24652f309f1e4484b10fa825e498..de770c10da3d62dbca565303d0a68ac54baa74ba 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -691,15 +691,14 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
 {
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&smu_v13_0_0_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         smu_v13_0_0_dpm_features.bits);
 }
 
 static int smu_v13_0_0_system_features_control(struct smu_context *smu,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
index 9a34e5460b35a628979015e0200fc784b6081205..3d60d3c1e5858be5b0543471a573866cbde349ec 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
@@ -52,10 +52,13 @@
 #define SMU_13_0_12_FEA_MAP(smu_feature, smu_13_0_12_feature)                    \
        [smu_feature] = { 1, (smu_13_0_12_feature) }
 
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE                                                        \
-       (FEATURE_MASK(FEATURE_DATA_CALCULATION) |                              \
-        FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_FCLK))
+static const struct smu_feature_bits smu_v13_0_12_dpm_features = {
+       .bits = {
+               SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATION),
+               SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK),
+               SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK)
+       }
+};
 
 #define NUM_JPEG_RINGS_FW      10
 #define NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics) \
@@ -199,14 +202,14 @@ void smu_v13_0_12_tables_fini(struct smu_context *smu)
 }
 
 static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu,
-                                        uint64_t *feature_mask)
+                                        struct smu_feature_bits *feature_mask)
 {
        int ret;
 
        ret = smu_cmn_get_enabled_mask(smu, feature_mask);
 
        if (ret == -EIO) {
-               *feature_mask = 0;
+               smu_feature_bits_clearall(feature_mask);
                ret = 0;
        }
 
@@ -372,14 +375,15 @@ int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu)
 bool smu_v13_0_12_is_dpm_running(struct smu_context *smu)
 {
        int ret;
-       uint64_t feature_enabled;
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_v13_0_12_get_enabled_mask(smu, &feature_enabled);
 
        if (ret)
                return false;
 
-       return !!(feature_enabled & SMC_DPM_FEATURE);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         smu_v13_0_12_dpm_features.bits);
 }
 
 int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 741762f4bd2cf42b3bbff013d5c6ae1070f9082d..75b90ac0c29c5978f47e503fae3680d080f6d633 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -213,16 +213,15 @@ static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu)
 static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu)
 {
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&smu_v13_0_4_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         smu_v13_0_4_dpm_features.bits);
 }
 
 static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index 7311162e50f005e629f6250cfa26d48ddc9c9269..8ee5002e3d6b241b5f4edb29207c922bd3dad937 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -232,16 +232,15 @@ static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
 {
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&smu_v13_0_5_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         smu_v13_0_5_dpm_features.bits);
 }
 
 static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 97866e5701921a7af805f14471eceaf6a416ecb2..be7d77eee2b079965685c4b38a7ff62dd8b613bc 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2272,14 +2272,14 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu,
 }
 
 static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
-                                       uint64_t *feature_mask)
+                                       struct smu_feature_bits *feature_mask)
 {
        int ret;
 
        ret = smu_cmn_get_enabled_mask(smu, feature_mask);
 
        if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
-               *feature_mask = 0;
+               smu_feature_bits_clearall(feature_mask);
                ret = 0;
        }
 
@@ -2289,8 +2289,7 @@ static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
 static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
 {
        int ret;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
                return smu_v13_0_12_is_dpm_running(smu);
@@ -2300,8 +2299,8 @@ static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&smu_v13_0_6_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         smu_v13_0_6_dpm_features.bits);
 }
 
 static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index eeff6c874635d711443dedefe9a3ff0967dd1577..fe3d6bfe681217c6687b20300a28090070fcd97a 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -699,15 +699,14 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
 {
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&smu_v13_0_7_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         smu_v13_0_7_dpm_features.bits);
 }
 
 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 2331dbb9181ab9d3b421e673b8372fca9fe4bb52..f9789b1fcbf83af116f0a977d03a4cd8040af36d 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -259,16 +259,15 @@ static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 static bool yellow_carp_is_dpm_running(struct smu_context *smu)
 {
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&yellow_carp_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         yellow_carp_dpm_features.bits);
 }
 
 static int yellow_carp_post_smu_init(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index 019e43fdecd63ebbdd2d2acb11c0a149ee4a5127..dbdf7653cc5349716bd492a782ab42881befb6a8 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -472,16 +472,15 @@ static int smu_v14_0_0_read_sensor(struct smu_context *smu,
 static bool smu_v14_0_0_is_dpm_running(struct smu_context *smu)
 {
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&smu_v14_0_0_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         smu_v14_0_0_dpm_features.bits);
 }
 
 static int smu_v14_0_0_set_watermarks_table(struct smu_context *smu,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index eb8bad2de1cc274572bd95b21d3e489c0dbcee34..becfd356b4e716a090ec95f948901667b69bbadc 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -589,15 +589,14 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu)
 static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu)
 {
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&smu_v14_0_2_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         smu_v14_0_2_dpm_features.bits);
 }
 
 static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
index d66e9a1a0ef8311da75b5dbd1c899ca7258d78b6..c3f22844ba2f16a3fb7b1b97753d418d54432ead 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
@@ -446,16 +446,15 @@ static int smu_v15_0_0_read_sensor(struct smu_context *smu,
 static bool smu_v15_0_0_is_dpm_running(struct smu_context *smu)
 {
        int ret = 0;
-       uint64_t feature_enabled;
-       uint32_t feature_mask[2];
+       struct smu_feature_bits feature_enabled;
 
        ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 
        if (ret)
                return false;
 
-       smu_feature_bits_to_arr32(&smu_v15_0_0_dpm_features, feature_mask, 64);
-       return !!(feature_enabled & *(uint64_t *)feature_mask);
+       return smu_feature_bits_test_mask(&feature_enabled,
+                                         smu_v15_0_0_dpm_features.bits);
 }
 
 static int smu_v15_0_0_set_watermarks_table(struct smu_context *smu,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 9bb7e3760c0ff3f9a407d077ad99badf41de3149..a9e0b52bc739d795572b45570a65720e62e3d467 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -690,7 +690,7 @@ int smu_cmn_feature_is_supported(struct smu_context *smu,
 }
 
 static int __smu_get_enabled_features(struct smu_context *smu,
-                              uint64_t *enabled_features)
+                                     struct smu_feature_bits *enabled_features)
 {
        return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features);
 }
@@ -699,7 +699,7 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu,
                               enum smu_feature_mask mask)
 {
        struct amdgpu_device *adev = smu->adev;
-       uint64_t enabled_features;
+       struct smu_feature_bits enabled_features;
        int feature_id;
 
        if (__smu_get_enabled_features(smu, &enabled_features)) {
@@ -712,7 +712,8 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu,
         * enabled. Also considering they have no feature_map available, the
         * check here can avoid unwanted feature_map check below.
         */
-       if (enabled_features == ULLONG_MAX)
+       if (smu_feature_bits_full(&enabled_features,
+                                 smu->smu_feature.feature_num))
                return 1;
 
        feature_id = smu_cmn_to_asic_specific_index(smu,
@@ -721,7 +722,7 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu,
        if (feature_id < 0)
                return 0;
 
-       return test_bit(feature_id, (unsigned long *)&enabled_features);
+       return smu_feature_bits_is_set(&enabled_features, feature_id);
 }
 
 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
@@ -763,45 +764,38 @@ bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
 }
 
 int smu_cmn_get_enabled_mask(struct smu_context *smu,
-                            uint64_t *feature_mask)
+                            struct smu_feature_bits *feature_mask)
 {
-       uint32_t *feature_mask_high;
-       uint32_t *feature_mask_low;
+       uint32_t features[2];
        int ret = 0, index = 0;
 
        if (!feature_mask)
                return -EINVAL;
 
-       feature_mask_low = &((uint32_t *)feature_mask)[0];
-       feature_mask_high = &((uint32_t *)feature_mask)[1];
-
        index = smu_cmn_to_asic_specific_index(smu,
                                                CMN2ASIC_MAPPING_MSG,
                                                SMU_MSG_GetEnabledSmuFeatures);
        if (index > 0) {
-               ret = smu_cmn_send_smc_msg_with_param(smu,
-                                                     SMU_MSG_GetEnabledSmuFeatures,
-                                                     0,
-                                                     feature_mask_low);
+               ret = smu_cmn_send_smc_msg_with_param(
+                       smu, SMU_MSG_GetEnabledSmuFeatures, 0, &features[0]);
                if (ret)
                        return ret;
 
-               ret = smu_cmn_send_smc_msg_with_param(smu,
-                                                     SMU_MSG_GetEnabledSmuFeatures,
-                                                     1,
-                                                     feature_mask_high);
+               ret = smu_cmn_send_smc_msg_with_param(
+                       smu, SMU_MSG_GetEnabledSmuFeatures, 1, &features[1]);
        } else {
-               ret = smu_cmn_send_smc_msg(smu,
-                                          SMU_MSG_GetEnabledSmuFeaturesHigh,
-                                          feature_mask_high);
+               ret = smu_cmn_send_smc_msg(
+                       smu, SMU_MSG_GetEnabledSmuFeaturesHigh, &features[1]);
                if (ret)
                        return ret;
 
-               ret = smu_cmn_send_smc_msg(smu,
-                                          SMU_MSG_GetEnabledSmuFeaturesLow,
-                                          feature_mask_low);
+               ret = smu_cmn_send_smc_msg(
+                       smu, SMU_MSG_GetEnabledSmuFeaturesLow, &features[0]);
        }
 
+       if (!ret)
+               smu_feature_bits_from_arr32(feature_mask, features, 64);
+
        return ret;
 }
 
@@ -886,7 +880,8 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
                                   char *buf)
 {
        int8_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)];
-       uint64_t feature_mask;
+       struct smu_feature_bits feature_mask;
+       uint32_t features[2];
        int i, feature_index;
        uint32_t count = 0;
        size_t size = 0;
@@ -894,8 +889,10 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
        if (__smu_get_enabled_features(smu, &feature_mask))
                return 0;
 
-       size =  sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n",
-                       upper_32_bits(feature_mask), lower_32_bits(feature_mask));
+       /* TBD: Need to handle for > 64 bits */
+       smu_feature_bits_to_arr32(&feature_mask, features, 64);
+       size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n",
+                            features[1], features[0]);
 
        memset(sort_feature, -1, sizeof(sort_feature));
 
@@ -916,12 +913,13 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
                if (sort_feature[feature_index] < 0)
                        continue;
 
-               size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n",
-                               count++,
-                               smu_get_feature_name(smu, sort_feature[feature_index]),
-                               feature_index,
-                               !!test_bit(feature_index, (unsigned long *)&feature_mask) ?
-                               "enabled" : "disabled");
+               size += sysfs_emit_at(
+                       buf, size, "%02d. %-20s (%2d) : %s\n", count++,
+                       smu_get_feature_name(smu, sort_feature[feature_index]),
+                       feature_index,
+                       smu_feature_bits_is_set(&feature_mask, feature_index) ?
+                               "enabled" :
+                               "disabled");
        }
 
        return size;
@@ -931,7 +929,8 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
                                uint64_t new_mask)
 {
        int ret = 0;
-       uint64_t feature_mask;
+       struct smu_feature_bits feature_mask;
+       uint64_t feature_mask_u64;
        uint64_t feature_2_enabled = 0;
        uint64_t feature_2_disabled = 0;
 
@@ -939,8 +938,9 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
        if (ret)
                return ret;
 
-       feature_2_enabled  = ~feature_mask & new_mask;
-       feature_2_disabled = feature_mask & ~new_mask;
+       feature_mask_u64 = *(uint64_t *)feature_mask.bits;
+       feature_2_enabled = ~feature_mask_u64 & new_mask;
+       feature_2_disabled = feature_mask_u64 & ~new_mask;
 
        if (feature_2_enabled) {
                ret = smu_cmn_feature_update_enable_state(smu,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index 92ad2ece7a3630a53dceac2ce18446af7ca11c50..b7bfddc65fb217896382fdb0c3e366528b6d792c 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -141,7 +141,7 @@ bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
                                enum smu_clk_type clk_type);
 
 int smu_cmn_get_enabled_mask(struct smu_context *smu,
-                            uint64_t *feature_mask);
+                            struct smu_feature_bits *feature_mask);
 
 uint64_t smu_cmn_get_indep_throttler_status(
                                        const unsigned long dep_status,