MIPS: mipsregs: Set proper ISA level for virt extensions

[ Upstream commit a640d6762a7d404644201ebf6d2a078e8dc84f97 ]

c994a3ec7ecc ("MIPS: set mips32r5 for virt extensions") setted
some instructions in virt extensions to ISA level mips32r5.

However TLB related vz instructions was leftover, also this
shouldn't be done to a R5 or R6 kernel buid.

Reorg macros to set ISA level as needed when _ASM_SET_VIRT
is called.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: WangYuli <wangyuli@uniontech.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 99eeafe6dcabdbc4e1c17f7faf6b0ceb6840e61f..c60e72917a2813c8307a1545d3d6674b5a7fc502 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2078,7 +2078,14 @@ do {                                                                     \
                _ASM_INSN_IF_MIPS(0x4200000c)                           \
                _ASM_INSN32_IF_MM(0x0000517c)
 #else  /* !TOOLCHAIN_SUPPORTS_VIRT */
-#define _ASM_SET_VIRT ".set\tvirt\n\t"
+#if MIPS_ISA_REV >= 5
+#define _ASM_SET_VIRT_ISA
+#elif defined(CONFIG_64BIT)
+#define _ASM_SET_VIRT_ISA ".set\tmips64r5\n\t"
+#else
+#define _ASM_SET_VIRT_ISA ".set\tmips32r5\n\t"
+#endif
+#define _ASM_SET_VIRT _ASM_SET_VIRT_ISA ".set\tvirt\n\t"
 #define _ASM_SET_MFGC0 _ASM_SET_VIRT
 #define _ASM_SET_DMFGC0        _ASM_SET_VIRT
 #define _ASM_SET_MTGC0 _ASM_SET_VIRT
@@ -2099,7 +2106,6 @@ do {                                                                      \
 ({ int __res;                                                          \
        __asm__ __volatile__(                                           \
                ".set\tpush\n\t"                                        \
-               ".set\tmips32r5\n\t"                                    \
                _ASM_SET_MFGC0                                          \
                "mfgc0\t%0, " #source ", %1\n\t"                        \
                _ASM_UNSET_MFGC0                                        \
@@ -2113,7 +2119,6 @@ do {                                                                      \
 ({ unsigned long long __res;                                           \
        __asm__ __volatile__(                                           \
                ".set\tpush\n\t"                                        \
-               ".set\tmips64r5\n\t"                                    \
                _ASM_SET_DMFGC0                                         \
                "dmfgc0\t%0, " #source ", %1\n\t"                       \
                _ASM_UNSET_DMFGC0                                       \
@@ -2127,7 +2132,6 @@ do {                                                                      \
 do {                                                                   \
        __asm__ __volatile__(                                           \
                ".set\tpush\n\t"                                        \
-               ".set\tmips32r5\n\t"                                    \
                _ASM_SET_MTGC0                                          \
                "mtgc0\t%z0, " #register ", %1\n\t"                     \
                _ASM_UNSET_MTGC0                                        \
@@ -2140,7 +2144,6 @@ do {                                                                      \
 do {                                                                   \
        __asm__ __volatile__(                                           \
                ".set\tpush\n\t"                                        \
-               ".set\tmips64r5\n\t"                                    \
                _ASM_SET_DMTGC0                                         \
                "dmtgc0\t%z0, " #register ", %1\n\t"                    \
                _ASM_UNSET_DMTGC0                                       \