#include "hw/arm/aspeed_ast1700.h"
#define AST2700_SOC_LTPI_SIZE 0x01000000
+#define AST1700_SOC_SRAM_SIZE 0x00040000
enum {
+ ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
};
static const hwaddr aspeed_ast1700_io_memmap[] = {
+ [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
};
{
AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ char dev_name[32];
/* Occupy memory space for all controllers in AST1700 */
memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
AST2700_SOC_LTPI_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
+ /* SRAM */
+ snprintf(dev_name, sizeof(dev_name), "aspeed.ioexp-sram.%d", s->board_idx);
+ memory_region_init_ram(&s->sram, OBJECT(s), dev_name,
+ AST1700_SOC_SRAM_SIZE, errp);
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SRAM],
+ &s->sram);
+
/* UART */
qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2);
qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400);
return;
}
+static const Property aspeed_ast1700_props[] = {
+ DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0),
+};
+
static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = aspeed_ast1700_realize;
+ device_class_set_props(dc, aspeed_ast1700_props);
}
static const TypeInfo aspeed_ast1700_info = {