drm: rcar-du: lvds: Set LVEN and LVRES bits together on D3

[ Upstream commit 00d082cc4ea6e42ec4fed832a1020231bb1ca150 ]

On the D3 SoC the LVDS PHY must be enabled in the same register write
that enables the LVDS output. Skip writing the LVEN bit independently
on that platform, it will be set by the write that sets LVRES.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
index 7ef97b2a6edaa63a2c8b0f4638c1e5f18f4f2dc5..f0314790333ba0c68e1ed3ea722d393c608660c5 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
+++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
@@ -485,9 +485,13 @@ static void rcar_lvds_enable(struct drm_bridge *bridge)
        }
 
        if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
-               /* Turn on the LVDS PHY. */
+               /*
+                * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
+                * set at the same time, so don't write the register yet.
+                */
                lvdcr0 |= LVDCR0_LVEN;
-               rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+               if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
+                       rcar_lvds_write(lvds, LVDCR0, lvdcr0);
        }
 
        if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {