Add clock definitions for XSPI0/1 to both R9A09G077 and R9A09G087 SoCs.
These definitions are required for describing XSPI devices in DT
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251028165127.991351-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
#define R9A09G077_ETCLKC 19
#define R9A09G077_ETCLKD 20
#define R9A09G077_ETCLKE 21
+#define R9A09G077_XSPI_CLK0 22
+#define R9A09G077_XSPI_CLK1 23
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
#define R9A09G087_ETCLKC 19
#define R9A09G087_ETCLKD 20
#define R9A09G087_ETCLKE 21
+#define R9A09G087_XSPI_CLK0 22
+#define R9A09G087_XSPI_CLK1 23
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */