Bug #360425 - arm64 unsupported instruction ldpsw tests.

Add tests for ldpsw implementation VEX svn r3212.

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15830

diff --git a/NEWS b/NEWS
index 0072d027d0e4767b32b402c818df93e0fdf3bc93..134b84aebf3960d84362bf5d8fd9c5887eb2f1fd 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -81,6 +81,7 @@ where XXXXXX is the bug number as listed below.
 359829  PowerPC test none/tests/ppc64/test_isa_2_07.c uninitialized memory
         references was fixed.
 359871  Incorrect mask handling in ppoll
+360425  arm64 unsupported instruction ldpsw
 360519  none/tests/arm64/memory.vgtest might fail with newer gcc
 
 n-i-bz Fix incorrect (or infinite loop) unwind on RHEL7 x86 and amd64

diff --git a/none/tests/arm64/memory.c b/none/tests/arm64/memory.c
index cbf31fd7eee94873ab885fded8be35547c68f51f..91949ac87f10044a2e119cdb9054e46a1762fa41 100644 (file)
--- a/none/tests/arm64/memory.c
+++ b/none/tests/arm64/memory.c
@@ -280,6 +280,18 @@ TESTINST2_hide2("ldarb w21, [x22]", AREA_MID, x21,x22,0);
 
 ////////////////////////////////////////////////////////////////
 printf("STL{R,RH,RB} (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+// TESTINST2_hide2 allows use of x28 as scratch
+printf("LDPSW (immediate, simm7)\n");
+
+TESTINST2_hide2("ldpsw x21, x28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+
 } /* end of test_memory_old() */
 
 
@@ -1608,6 +1620,12 @@ MEM_TEST("prfm pstl2strm, [x5,w6,uxtw #3]", 12, 4);
 MEM_TEST("prfm pstl3keep, [x5,w6,sxtw #0]", 12, 4);
 MEM_TEST("prfm pstl3strm, [x5,w6,sxtw #3]",  12, -4);
 
+////////////////////////////////////////////////////////////////
+printf("LDPSW (immediate, simm7)\n");
+MEM_TEST("ldpsw x13, x23, [x5], #-24",   0, 0);
+MEM_TEST("ldpsw x13, x23, [x5, #-40]!",  0, 0);
+MEM_TEST("ldpsw x13, x23, [x5, #-40]",   0, 0);
+
 } /* end of test_memory2() */
 
 ////////////////////////////////////////////////////////////////

diff --git a/none/tests/arm64/memory.stdout.exp b/none/tests/arm64/memory.stdout.exp
index eb6ec3f79610467204f5163e6f45e0243d1c3e13..be571080ffc46f7f0cb4d641a6c1766d1c2e7a60 100644 (file)
--- a/none/tests/arm64/memory.stdout.exp
+++ b/none/tests/arm64/memory.stdout.exp
@@ -98,6 +98,13 @@ ldar  w21, [x22] :: rd 00000000f3f2f1f0 rn (hidden), cin 0, nzcv 00000000
 ldarh w21, [x22] :: rd 000000000000f1f0 rn (hidden), cin 0, nzcv 00000000     
 ldarb w21, [x22] :: rd 00000000000000f0 rn (hidden), cin 0, nzcv 00000000     
 STL{R,RH,RB} (entirely MISSING)
+LDPSW (immediate, simm7)
+ldpsw x21, x28, [x22], #-24 ; add x21,x21,x28 :: rd ffffffffebe9e7e4 rn (hidden), cin 0, nzcv 00000000     
+ldpsw x21, x28, [x22], #-24 ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000     
+ldpsw x21, x28, [x22, #-40]! ; add x21,x21,x28 :: rd ffffffff9b999794 rn (hidden), cin 0, nzcv 00000000     
+ldpsw x21, x28, [x22, #-40]! ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000     
+ldpsw x21, x28, [x22, #-40] ; add x21,x21,x28 :: rd ffffffff9b999794 rn (hidden), cin 0, nzcv 00000000     
+ldpsw x21, x28, [x22, #-40] ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000     
 LDR,STR (immediate, uimm12)ldr  x13, [x5, #24]  with  x5 = middle_of_block+-1,  x6=0
   [  0]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
   [ 16]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
@@ -26258,3 +26265,94 @@ prfm pstl3strm, [x5,w6,sxtw #3]  with  x5 = middle_of_block+12,  x6=-4
                  0  x5       (sub, base reg)
                  0  x6       (sub, index reg)
 
+LDPSW (immediate, simm7)
+ldpsw x13, x23, [x5], #-24  with  x5 = middle_of_block+0,  x6=0
+  [  0]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 16]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 32]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 48]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 64]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 80]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 96]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [112]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [128]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [144]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [160]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [176]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [192]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [208]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [224]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [240]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  5430cb99daf026bb  x13      (xor, xfer intreg #1)
+  58eb9b702726900d  x23      (xor, xfer intreg #2)
+  0000000000000000  v17.d[0] (xor, xfer vecreg #1)
+  0000000000000000  v17.d[1] (xor, xfer vecreg #1)
+  0000000000000000  v18.d[0] (xor, xfer vecreg #2)
+  0000000000000000  v18.d[1] (xor, xfer vecreg #2)
+  0000000000000000  v19.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v19.d[1] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[1] (xor, xfer vecreg #3)
+               -24  x5       (sub, base reg)
+                 0  x6       (sub, index reg)
+
+ldpsw x13, x23, [x5, #-40]!  with  x5 = middle_of_block+0,  x6=0
+  [  0]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 16]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 32]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 48]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 64]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 80]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 96]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [112]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [128]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [144]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [160]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [176]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [192]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [208]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [224]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [240]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  7f799c624bfa7f08  x13      (xor, xfer intreg #1)
+  3e7857cc51fd19f0  x23      (xor, xfer intreg #2)
+  0000000000000000  v17.d[0] (xor, xfer vecreg #1)
+  0000000000000000  v17.d[1] (xor, xfer vecreg #1)
+  0000000000000000  v18.d[0] (xor, xfer vecreg #2)
+  0000000000000000  v18.d[1] (xor, xfer vecreg #2)
+  0000000000000000  v19.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v19.d[1] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[1] (xor, xfer vecreg #3)
+               -40  x5       (sub, base reg)
+                 0  x6       (sub, index reg)
+
+ldpsw x13, x23, [x5, #-40]  with  x5 = middle_of_block+0,  x6=0
+  [  0]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 16]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 32]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 48]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 64]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 80]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [ 96]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [112]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [128]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [144]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [160]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [176]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [192]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [208]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [224]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  [240]  .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 
+  01ba3febe99768c0  x13      (xor, xfer intreg #1)
+  1cef424f7c21ff9b  x23      (xor, xfer intreg #2)
+  0000000000000000  v17.d[0] (xor, xfer vecreg #1)
+  0000000000000000  v17.d[1] (xor, xfer vecreg #1)
+  0000000000000000  v18.d[0] (xor, xfer vecreg #2)
+  0000000000000000  v18.d[1] (xor, xfer vecreg #2)
+  0000000000000000  v19.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v19.d[1] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[0] (xor, xfer vecreg #3)
+  0000000000000000  v20.d[1] (xor, xfer vecreg #3)
+                 0  x5       (sub, base reg)
+                 0  x6       (sub, index reg)
+