arm64: dts: freescale: imx93-phyboard-segin: Add EQOS Ethernet

Add support for the carrier-board Micrel KSZ8081 Ethernet PHY. This is a
10/100Mbit PHY connected to the EQOS interface and shares MDIO bus with
the Ethernet PHY located on the SoM (FEC interface).

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index 54e084e69706e8b25a1ac1aff350d9b03eb65171..c62cc06fad4b702ba443d19d95fad0a7d71ce174 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -89,6 +89,28 @@
        };
 };
 
+/* Ethernet */
+&eqos {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_eqos>;
+       phy-mode = "rmii";
+       phy-handle = <&ethphy2>;
+       assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+                                <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+       assigned-clock-rates = <100000000>, <50000000>;
+       status = "okay";
+};
+
+&mdio {
+       ethphy2: ethernet-phy@2 {
+               compatible = "ethernet-phy-id0022.1561";
+               reg = <2>;
+               clocks = <&clk IMX93_CLK_ENET_REF_PHY>;
+               clock-names = "rmii-ref";
+               micrel,led-mode = <1>;
+       };
+};
+
 /* CAN */
 &flexcan1 {
        pinctrl-names = "default";
@@ -173,6 +195,19 @@
 };
 
 &iomuxc {
+       pinctrl_eqos: eqosgrp {
+               fsl,pins = <
+                       MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000050e
+                       MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0          0x57e
+                       MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1          0x57e
+                       MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0          0x50e
+                       MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1          0x50e
+                       MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL    0x57e
+                       MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL    0x50e
+                       MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER              0x57e
+               >;
+       };
+
        pinctrl_flexcan1: flexcan1grp {
                fsl,pins = <
                        MX93_PAD_PDM_BIT_STREAM0__CAN1_RX       0x139e