x86/msr: Rename 'native_wrmsrl()' to 'native_wrmsrq()'

Suggested-by: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Juergen Gross <jgross@suse.com>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Xin Li <xin@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>

diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c
index 77bf05f06b9efaf0ab16e681905161d0fb9a8346..1b8a2415183b746d59e2eae52ab99b598203cd0b 100644 (file)
--- a/arch/x86/hyperv/ivm.c
+++ b/arch/x86/hyperv/ivm.c
@@ -115,7 +115,7 @@ static inline u64 rd_ghcb_msr(void)
 
 static inline void wr_ghcb_msr(u64 val)
 {
-       native_wrmsrl(MSR_AMD64_SEV_ES_GHCB, val);
+       native_wrmsrq(MSR_AMD64_SEV_ES_GHCB, val);
 }
 
 static enum es_result hv_ghcb_hv_call(struct ghcb *ghcb, u64 exit_code,

diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 695e569159c1d1fcbf469f8fe8ce1a0f366df996..263ea3dd0001cd22e042f2cb3a8bd783bcfacb1c 100644 (file)
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -61,7 +61,7 @@ static inline u32 intel_get_microcode_revision(void)
 {
        u32 rev, dummy;
 
-       native_wrmsrl(MSR_IA32_UCODE_REV, 0);
+       native_wrmsrq(MSR_IA32_UCODE_REV, 0);
 
        /* As documented in the SDM: Do a CPUID 1 here */
        native_cpuid_eax(1);

diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 4335f914d6f877a3990c43c27eb492443eea5264..20deb58308e5ea1883ebc2ea6ab297c2ad0522d6 100644 (file)
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -109,7 +109,7 @@ do {                                                        \
 #define native_wrmsr(msr, low, high)                   \
        __wrmsr(msr, low, high)
 
-#define native_wrmsrl(msr, val)                                \
+#define native_wrmsrq(msr, val)                                \
        __wrmsr((msr), (u32)((u64)(val)),               \
                       (u32)((u64)(val) >> 32))
 

diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h
index 658b690b2ccb7d627c6418b32cba5c3a7d959832..00b7e0398210e93c8a7901665cd4c98a68826b61 100644 (file)
--- a/arch/x86/include/asm/spec-ctrl.h
+++ b/arch/x86/include/asm/spec-ctrl.h
@@ -84,7 +84,7 @@ static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)
 static __always_inline void __update_spec_ctrl(u64 val)
 {
        __this_cpu_write(x86_spec_ctrl_current, val);
-       native_wrmsrl(MSR_IA32_SPEC_CTRL, val);
+       native_wrmsrq(MSR_IA32_SPEC_CTRL, val);
 }
 
 #ifdef CONFIG_SMP

diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index b61028cf5c8a3b3b4f7fc8099747d26f392df0c6..041dae089a3678d911e0a1b61a2c76660ea2368c 100644 (file)
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -602,7 +602,7 @@ static bool __apply_microcode_amd(struct microcode_amd *mc, u32 *cur_rev,
        if (!verify_sha256_digest(mc->hdr.patch_id, *cur_rev, (const u8 *)p_addr, psize))
                return false;
 
-       native_wrmsrl(MSR_AMD64_PATCH_LOADER, p_addr);
+       native_wrmsrq(MSR_AMD64_PATCH_LOADER, p_addr);
 
        if (x86_family(bsp_cpuid_1_eax) == 0x17) {
                unsigned long p_addr_end = p_addr + psize - 1;

diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index 819199bc0119b23fee8ae1ecd490d2fb6936dc4e..86e1047f738fe7e2f41ef50225ad0304e2c5d771 100644 (file)
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -320,7 +320,7 @@ static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci,
        }
 
        /* write microcode via MSR 0x79 */
-       native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
+       native_wrmsrq(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
 
        rev = intel_get_microcode_revision();
        if (rev != mc->hdr.rev)

diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 9b221bdd3c51335f59398fa42f2288ccfb7bea01..cd0d6c1fcf9cfc48fea8546f76d6bb04384db627 100644 (file)
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -382,7 +382,7 @@ static __always_inline void vmx_disable_fb_clear(struct vcpu_vmx *vmx)
 
        msr = __rdmsr(MSR_IA32_MCU_OPT_CTRL);
        msr |= FB_CLEAR_DIS;
-       native_wrmsrl(MSR_IA32_MCU_OPT_CTRL, msr);
+       native_wrmsrq(MSR_IA32_MCU_OPT_CTRL, msr);
        /* Cache the MSR value to avoid reading it later */
        vmx->msr_ia32_mcu_opt_ctrl = msr;
 }
@@ -393,7 +393,7 @@ static __always_inline void vmx_enable_fb_clear(struct vcpu_vmx *vmx)
                return;
 
        vmx->msr_ia32_mcu_opt_ctrl &= ~FB_CLEAR_DIS;
-       native_wrmsrl(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl);
+       native_wrmsrq(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl);
 }
 
 static void vmx_update_fb_clear_dis(struct kvm_vcpu *vcpu, struct vcpu_vmx *vmx)
@@ -6745,7 +6745,7 @@ static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
        vcpu->stat.l1d_flush++;
 
        if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
-               native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
+               native_wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
                return;
        }
 
@@ -7318,7 +7318,7 @@ void noinstr vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx,
         */
        if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS) ||
            vmx->spec_ctrl != hostval)
-               native_wrmsrl(MSR_IA32_SPEC_CTRL, hostval);
+               native_wrmsrq(MSR_IA32_SPEC_CTRL, hostval);
 
        barrier_nospec();
 }