Add support for the TEXASRU register. This register contains information on

transactional memory instruction summary information.  This register contains
the upper 32-bits of the transaction information.  Note, the valgrind
implementation of transactional memory instructions is limited.  Currently, the
contents of the TEXASRU register will always return 0.  The lower 64-bits of
the trasnaction information in the TEXASR register will contain the failure
information as setup by Valgrind.

This commit contains the changes needed to support the TEXASRU register on
PPC64.

This support requires changing the value of MAX_REG_WRITE_SIZE in
memcheck/mc_main.c from 1696 to 1712.  The change is made in the corresponding
valgrind commit.

This patch addresses Bugzilla 346474

git-svn-id: svn://svn.valgrind.org/vex/trunk@3143

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 6a29c470f6fca9088da4de6db0e1de2b78264a4c..b1326da0c34b8eeba00db10084508584fb8a591d 100644 (file)
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -286,6 +286,7 @@ static void* fnptr_to_fnentry( const VexAbiInfo* vbi, void* f )
 #define OFFB_NRADDR_GPR2 offsetofPPCGuestState(guest_NRADDR_GPR2)
 #define OFFB_TFHAR       offsetofPPCGuestState(guest_TFHAR)
 #define OFFB_TEXASR      offsetofPPCGuestState(guest_TEXASR)
+#define OFFB_TEXASRU     offsetofPPCGuestState(guest_TEXASRU)
 #define OFFB_TFIAR       offsetofPPCGuestState(guest_TFIAR)
 
 
@@ -436,6 +437,7 @@ typedef enum {
     PPC_GST_TFHAR,  // Transactional Failure Handler Address Register
     PPC_GST_TFIAR,  // Transactional Failure Instruction Address Register
     PPC_GST_TEXASR, // Transactional EXception And Summary Register
+    PPC_GST_TEXASRU, // Transactional EXception And Summary Register Upper
     PPC_GST_MAX
 } PPC_GST;
 
@@ -2739,6 +2741,9 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg )
    case PPC_GST_TEXASR:
       return IRExpr_Get( OFFB_TEXASR, ty );
 
+   case PPC_GST_TEXASRU:
+      return IRExpr_Get( OFFB_TEXASRU, ty );
+
    case PPC_GST_TFIAR:
       return IRExpr_Get( OFFB_TFIAR, ty );
 
@@ -2907,6 +2912,12 @@ static void putGST ( PPC_GST reg, IRExpr* src )
       vassert( ty_src == Ity_I64 );
       stmt( IRStmt_Put( OFFB_TEXASR, src ) );
       break;
+
+   case PPC_GST_TEXASRU:
+      vassert( ty_src == Ity_I32 );
+      stmt( IRStmt_Put( OFFB_TEXASRU, src ) );
+      break;
+
    case PPC_GST_TFIAR:
       vassert( ty_src == Ity_I64 );
       stmt( IRStmt_Put( OFFB_TFIAR, src ) );
@@ -3337,9 +3348,10 @@ static ULong generate_TMreason( UInt failure_code,
 static void storeTMfailure( Addr64 err_address, ULong tm_reason,
                             Addr64 handler_address )
 {
-   putGST( PPC_GST_TFIAR,  mkU64( err_address ) );
-   putGST( PPC_GST_TEXASR, mkU64( tm_reason ) );
-   putGST( PPC_GST_TFHAR,  mkU64( handler_address ) );
+   putGST( PPC_GST_TFIAR,   mkU64( err_address ) );
+   putGST( PPC_GST_TEXASR,  mkU64( tm_reason ) );
+   putGST( PPC_GST_TEXASRU, mkU32( 0 ) );
+   putGST( PPC_GST_TFHAR,   mkU64( handler_address ) );
 }
 
 /*------------------------------------------------------------*/
@@ -7115,6 +7127,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
          DIP("mfspr r%u (TEXASR)\n", rD_addr);
          putIReg( rD_addr, getGST( PPC_GST_TEXASR) );
          break;
+      case 0x83:  // 131
+         DIP("mfspr r%u (TEXASRU)\n", rD_addr);
+         putIReg( rD_addr, getGST( PPC_GST_TEXASRU) );
+         break;
       case 0x100: 
          DIP("mfvrsave r%u\n", rD_addr);
          putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_VRSAVE ),

diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h
index 35dd318dac0ea1419acfe3acee7287b1c1cf3bb6..3c2fd9e3b7bfff0bdcd15b8bfd2c88097d75d0e1 100644 (file)
--- a/VEX/pub/libvex_guest_ppc32.h
+++ b/VEX/pub/libvex_guest_ppc32.h
@@ -241,9 +241,10 @@ typedef
       /* 1360 */ ULong guest_TFHAR;     // Transaction Failure Handler Address Register 
       /* 1368 */ ULong guest_TEXASR;    // Transaction EXception And Summary Register
       /* 1376 */ ULong guest_TFIAR;     // Transaction Failure Instruction Address Register
+      /* 1384 */ UInt  guest_TEXASRU;   // Transaction EXception And Summary Register Upper
 
       /* Padding to make it have an 16-aligned size */
-      /* 1384 */ UInt  padding2;
+      /* 1388 */ UInt  padding2;
 
    }
    VexGuestPPC32State;

diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h
index 9a4caedee2ccf47dc47bde63196d8ce175ca97b5..13a3540f353ada097e60b5ff2702756ce565e1e8 100644 (file)
--- a/VEX/pub/libvex_guest_ppc64.h
+++ b/VEX/pub/libvex_guest_ppc64.h
@@ -282,6 +282,12 @@ typedef
       /* 1656 */ ULong guest_TFHAR;     // Transaction Failure Handler Address Register 
       /* 1664 */ ULong guest_TEXASR;    // Transaction EXception And Summary Register
       /* 1672 */ ULong guest_TFIAR;     // Transaction Failure Instruction Address Register
+      /* 1680 */ UInt  guest_TEXASRU;   // Transaction EXception And Summary Register Upper
+
+      /* Padding to make it have an 16-aligned size */
+      /* 1684 */  UInt  padding1;
+      /* 1688 */  UInt  padding2;
+      /* 1692 */  UInt  padding3;
 
    }
    VexGuestPPC64State;