arm64: dts: renesas: r9a07g054: Correct GICD and GICR sizes

[ Upstream commit 45afa9eacb59b258d2e53c7f63430ea1e8344803 ]

The RZ/V2L SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB
for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU.

Fixes: 7c2b8198f4f32 ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20240730122436.350013-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index a2318478a66ba79e4c975fdd1e2baa41db9f061b..66894b676c01ec01ff034acc81115e940c00a25a 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -1051,8 +1051,8 @@
                        #interrupt-cells = <3>;
                        #address-cells = <0>;
                        interrupt-controller;
-                       reg = <0x0 0x11900000 0 0x40000>,
-                             <0x0 0x11940000 0 0x60000>;
+                       reg = <0x0 0x11900000 0 0x20000>,
+                             <0x0 0x11940000 0 0x40000>;
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
                };