EDAC/sb_edac: Fix top-of-high-memory value for Broadwell/Haswell

commit 537bddd069c743759addf422d0b8f028ff0f8dbc upstream.

The computation of TOHM is off by one bit. This missed bit results in
too low a value for TOHM, which can cause errors in regular memory to
incorrectly report:

  EDAC MC0: 1 CE Error at MMIOH area, on addr 0x000000207fffa680 on any memory

Fixes: 50d1bb93672f ("sb_edac: add support for Haswell based systems")
Cc: stable@vger.kernel.org
Reported-by: Meeta Saggi <msaggi@purestorage.com>
Signed-off-by: Eric Badger <ebadger@purestorage.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20211010170127.848113-1-ebadger@purestorage.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index a4e1f6939c395de89fa49558c6313f251e3e3030..a2ad988c9bdc6e29715f0fcd828c496d0f16b352 100644 (file)
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -848,7 +848,7 @@ static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
        pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
        rc = ((reg << 6) | rc) << 26;
 
-       return rc | 0x1ffffff;
+       return rc | 0x3ffffff;
 }
 
 static u64 haswell_rir_limit(u32 reg)