arm64: dts: nuvoton: Add pinctrl

This is critical to support multifunction pins shared between devices as
well as generic GPIOs.

Signed-off-by: William A. Kennington III <william@wkennington.com>
Link: https://patch.msgid.link/20250416015902.2091251-1-william@wkennington.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://lore.kernel.org/r/20250515-nuvoton-arm64-dt-v1-1-25769b8c1509@codeconstruct.com.au
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
index ecd171b2feba488b486cdc72708420fca6fc11c8..fead4dde590dfff3f7d28a47c2b883462a6e51eb 100644 (file)
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -176,4 +176,69 @@
                        };
                };
        };
+
+       pinctrl: pinctrl@f0010000 {
+               compatible = "nuvoton,npcm845-pinctrl";
+               ranges = <0x0 0x0 0xf0010000 0x8000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               nuvoton,sysgcr = <&gcr>;
+               status = "okay";
+               gpio0: gpio@f0010000 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       reg = <0x0 0xB0>;
+                       interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-ranges = <&pinctrl 0 0 32>;
+               };
+               gpio1: gpio@f0011000 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       reg = <0x1000 0xB0>;
+                       interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-ranges = <&pinctrl 0 32 32>;
+               };
+               gpio2: gpio@f0012000 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       reg = <0x2000 0xB0>;
+                       interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-ranges = <&pinctrl 0 64 32>;
+               };
+               gpio3: gpio@f0013000 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       reg = <0x3000 0xB0>;
+                       interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-ranges = <&pinctrl 0 96 32>;
+               };
+               gpio4: gpio@f0014000 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       reg = <0x4000 0xB0>;
+                       interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-ranges = <&pinctrl 0 128 32>;
+               };
+               gpio5: gpio@f0015000 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       reg = <0x5000 0xB0>;
+                       interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-ranges = <&pinctrl 0 160 32>;
+               };
+               gpio6: gpio@f0016000 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       reg = <0x6000 0xB0>;
+                       interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-ranges = <&pinctrl 0 192 32>;
+               };
+               gpio7: gpio@f0017000 {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       reg = <0x7000 0xB0>;
+                       interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-ranges = <&pinctrl 0 224 32>;
+               };
+       };
 };