]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: qcom: kodiak: Fix PCIe1 PHY ref clock voting
authorKrishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Fri, 23 Jan 2026 12:12:27 +0000 (17:42 +0530)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sun, 17 May 2026 15:16:32 +0000 (17:16 +0200)
commit 30e8b6d42e8988eaaf0c2efd8c3797cb3884faea upstream.

GCC_PCIE_CLKREF_EN controls a repeater that provides the reference clock
only to the PCIe0 PHY. PCIe1 PHY receives its refclk directly from the CXO
source.

If the PCIe1 driver in HLOS votes for or against GCC_PCIE_CLKREF_EN, it
will inadvertently modify the refclk to PCIe0 as well. Since PCIe0 is
managed by WPSS while PCIe1 is managed in HLOS, there is no mechanism to
coordinate these votes. As a result, HLOS may disable this repeater
during suspend and cut off the PCIe0 PHY refclk while PCIe0 is still
active.

Replace the unused GCC_PCIE_CLKREF_EN clock entry with RPMH_CXO_CLK to
reflect the actual hardware wiring and prevent unintended changes to
PCIe0 clocking.

Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes")
Cc: stable@vger.kernel.org
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260123-fix_pcie1_phy_clk-v1-1-38f82ea01792@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arm64/boot/dts/qcom/kodiak.dtsi

index 6079e67ea829b5233bb87fdcb37d8a05d30fb87b..ba0f7e5c89a0deec592da25eda85b93d727277e1 100644 (file)
                        reg = <0 0x01c0e000 0 0x1000>;
                        clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
                                 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
-                                <&gcc GCC_PCIE_CLKREF_EN>,
+                                <&rpmhcc RPMH_CXO_CLK>,
                                 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
                                 <&gcc GCC_PCIE_1_PIPE_CLK>;
                        clock-names = "aux",