re PR target/81471 (internal compiler error: in curr_insn_transform, at lra-constrain...

	PR target/81471
	* config/i386/i386.md (rorx_immediate_operand): New mode attribute.
	(*bmi2_rorx<mode>3_1): Use rorx_immediate_operand as
	operand 2 predicate.
	(*bmi2_rorxsi3_1_zext): Use const_0_to_31_operand as
	operand 2 predicate.
	(ror,rol -> rorx splitters): Use const_int_operand as
	operand 2 predicate.

testsuite/ChangeLog:

	PR target/81471
	* gcc.target/i386/pr81471.c: New test.

From-SVN: r250322

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d9437b99ff4f5dd575844e595b1b8f8cc143aa70..9d4c3b9c925c22b3a153c81808b347bba9c2cb55 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2017-07-18  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/81471
+       * config/i386/i386.md (rorx_immediate_operand): New mode attribute.
+       (*bmi2_rorx<mode>3_1): Use rorx_immediate_operand as
+       operand 2 predicate.
+       (*bmi2_rorxsi3_1_zext): Use const_0_to_31_operand as
+       operand 2 predicate.
+       (ror,rol -> rorx splitters): Use const_int_operand as
+       operand 2 predicate.
+
 2017-07-14  Uros Bizjak  <ubizjak@gmail.com>
 
        Backport from mainline
@@ -199,7 +210,7 @@
 
        PR target/80968
        * config/sparc/sparc.c (sparc_flat_expand_epilogue): Don't
-        emit frame blockage here.
+       emit frame blockage here.
        (sparc_expand_epilogue): Do it here.
        * config/sparc/sparc.md (return expander): Emit frame blockage
        for alloca here too.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index ae4cc0775cecabddb0933c7cbecae5ea33a2cea5..c2b25cfad513531ccf48d072e78b73e4499f9af6 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10455,10 +10455,15 @@
   split_double_mode (<DWI>mode, &operands[0], 1, &operands[4], &operands[5]);
 })
 
+(define_mode_attr rorx_immediate_operand
+       [(SI "const_0_to_31_operand")
+        (DI "const_0_to_63_operand")])
+
 (define_insn "*bmi2_rorx<mode>3_1"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
-       (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
-                       (match_operand:QI 2 "immediate_operand" "<S>")))]
+       (rotatert:SWI48
+         (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+         (match_operand:QI 2 "<rorx_immediate_operand>" "<S>")))]
   "TARGET_BMI2"
   "rorx\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "rotatex")
@@ -10501,7 +10506,7 @@
 (define_split
   [(set (match_operand:SWI48 0 "register_operand")
        (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
-                     (match_operand:QI 2 "immediate_operand")))
+                     (match_operand:QI 2 "const_int_operand")))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_BMI2 && reload_completed"
   [(set (match_dup 0)
@@ -10515,7 +10520,7 @@
 (define_split
   [(set (match_operand:SWI48 0 "register_operand")
        (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
-                       (match_operand:QI 2 "immediate_operand")))
+                       (match_operand:QI 2 "const_int_operand")))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_BMI2 && reload_completed"
   [(set (match_dup 0)
@@ -10525,7 +10530,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI
          (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
-                      (match_operand:QI 2 "immediate_operand" "I"))))]
+                      (match_operand:QI 2 "const_0_to_31_operand" "I"))))]
   "TARGET_64BIT && TARGET_BMI2"
   "rorx\t{%2, %1, %k0|%k0, %1, %2}"
   [(set_attr "type" "rotatex")
@@ -10569,7 +10574,7 @@
   [(set (match_operand:DI 0 "register_operand")
        (zero_extend:DI
          (rotate:SI (match_operand:SI 1 "nonimmediate_operand")
-                    (match_operand:QI 2 "immediate_operand"))))
+                    (match_operand:QI 2 "const_int_operand"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && TARGET_BMI2 && reload_completed"
   [(set (match_dup 0)
@@ -10584,7 +10589,7 @@
   [(set (match_operand:DI 0 "register_operand")
        (zero_extend:DI
          (rotatert:SI (match_operand:SI 1 "nonimmediate_operand")
-                      (match_operand:QI 2 "immediate_operand"))))
+                      (match_operand:QI 2 "const_int_operand"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && TARGET_BMI2 && reload_completed"
   [(set (match_dup 0)

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e0345251cb26f3e1a2a065728d36fec7b9a43f7d..936b4537475e67df690ecea00a82868f46bed88b 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-07-18  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/81471
+       * gcc.target/i386/pr81471.c: New test.
+
 2017-07-14  Uros Bizjak  <ubizjak@gmail.com>
 
        Backport from mainline

diff --git a/gcc/testsuite/gcc.target/i386/pr81471.c b/gcc/testsuite/gcc.target/i386/pr81471.c
new file mode 100644 (file)
index 0000000..68b4497
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr81471.c
@@ -0,0 +1,13 @@
+/* PR target/81471 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi2" } */
+
+static inline unsigned int rotl (unsigned int x, int k)
+{
+  return (x << k) | (x >> (32 - k));
+}
+
+unsigned long long test (unsigned int z)
+{
+  return rotl (z, 55);
+}