clk: renesas: r9a09g057: Add reset entry for SYS

Add the missing reset entry for the `SYS` module in the clock driver. The
corresponding core clock entry for `SYS` is already present.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250102181839.352599-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index a45b4020996bd97316991c5a394f1896d1f3ba9a..7ef681dfcba5019dea0713477eb0123611cb3f78 100644 (file)
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -220,6 +220,7 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
 };
 
 static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
+       DEF_RST(3, 0, 1, 1),            /* SYS_0_PRESETN */
        DEF_RST(3, 6, 1, 7),            /* ICU_0_PRESETN_I */
        DEF_RST(6, 13, 2, 30),          /* GTM_0_PRESETZ */
        DEF_RST(6, 14, 2, 31),          /* GTM_1_PRESETZ */