ASoC: Intel: catpt: Complete coredump handling

An exception may occur during the firmware booting procedure.  In such
case the firmware sends COREDUMP_REQUESTS and expects the driver to dump
relevant information and finish with the COREDUMP_RELEASE write.

To distinguish such situation from generic timeout, always signal
fw_ready completion when a coredump request is received and translate
it to -EREMOTEIO in catpt_boot_firmware().

The "FW READY" print makes the success clearly visible even when
the event-traces are not enabled.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://patch.msgid.link/20260528083444.1439233-2-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/intel/catpt/ipc.c b/sound/soc/intel/catpt/ipc.c
index 2e3b7a5cbb9b252bf648f0d17700945ea29c540c..225757e6a7766c71d117e43395040a071642032c 100644 (file)
--- a/sound/soc/intel/catpt/ipc.c
+++ b/sound/soc/intel/catpt/ipc.c
@@ -210,6 +210,7 @@ static void catpt_dsp_process_response(struct catpt_dev *cdev, u32 header)
                memcpy_fromio(&config, cdev->lpe_ba + off, sizeof(config));
                trace_catpt_ipc_payload((u8 *)&config, sizeof(config));
 
+               dev_dbg(cdev->dev, "FW READY 0x%08x\n", header);
                catpt_ipc_arm(ipc, &config);
                complete(&cdev->fw_ready);
                return;
@@ -220,6 +221,13 @@ static void catpt_dsp_process_response(struct catpt_dev *cdev, u32 header)
                dev_err(cdev->dev, "ADSP device coredump received\n");
                ipc->ready = false;
                catpt_coredump(cdev);
+
+               if (catpt_readl_dram(cdev, COREDUMP) == CATPT_COREDUMP_REQUEST) {
+                       dev_dbg(cdev->dev, "releasing firmware from the coredump state\n");
+                       catpt_writel_dram(cdev, COREDUMP, CATPT_COREDUMP_RELEASE);
+               }
+
+               complete(&cdev->fw_ready);
                /* TODO: attempt recovery */
                break;
 

diff --git a/sound/soc/intel/catpt/loader.c b/sound/soc/intel/catpt/loader.c
index 432cb1f0ab4e234265a1d8ee08c6f1dedae3f2b8..75457187b614ff52e153256de01b96554aaa2394 100644 (file)
--- a/sound/soc/intel/catpt/loader.c
+++ b/sound/soc/intel/catpt/loader.c
@@ -624,6 +624,9 @@ int catpt_boot_firmware(struct catpt_dev *cdev, bool restore)
        if (!ret) {
                dev_err(cdev->dev, "firmware ready timeout\n");
                return -ETIMEDOUT;
+       /* Wake up does not mean FW is ready, an exception could occur. */
+       } else if (!cdev->ipc.ready) {
+               return -EREMOTEIO;
        }
 
        /* update sram pg & clock once done booting */

diff --git a/sound/soc/intel/catpt/registers.h b/sound/soc/intel/catpt/registers.h
index 6c1ad28c6d6922c02a2ee310ac3b0b944af3f181..64bd534a76ff460874ad4fc98c327eecc081dcd5 100644 (file)
--- a/sound/soc/intel/catpt/registers.h
+++ b/sound/soc/intel/catpt/registers.h
@@ -124,6 +124,11 @@
 #define CATPT_SSCR2_DEFAULT            0x0
 #define CATPT_SSPSP2_DEFAULT           0x0
 
+/* Coredump register and its states */
+#define CATPT_DRAM_COREDUMP            0x1F4
+#define CATPT_COREDUMP_REQUEST         UINT_MAX
+#define CATPT_COREDUMP_RELEASE         0
+
 /* Physically the same block, access address differs between host and dsp */
 #define CATPT_DSP_DRAM_OFFSET          0x400000
 #define catpt_to_host_offset(offset)   ((offset) & ~(CATPT_DSP_DRAM_OFFSET))
@@ -137,6 +142,8 @@
 
 /* registry I/O helpers */
 
+#define catpt_dram_addr(cdev) \
+       ((cdev)->lpe_ba + (cdev)->spec->host_dram_offset)
 #define catpt_shim_addr(cdev) \
        ((cdev)->lpe_ba + (cdev)->spec->host_shim_offset)
 #define catpt_dma_addr(cdev, dma) \
@@ -151,6 +158,11 @@
 #define catpt_writel_ssp(cdev, ssp, reg, val) \
        writel(val, catpt_ssp_addr(cdev, ssp) + (reg))
 
+#define catpt_readl_dram(cdev, reg) \
+       readl(catpt_dram_addr(cdev) + CATPT_DRAM_##reg)
+#define catpt_writel_dram(cdev, reg, val) \
+       writel(val, catpt_dram_addr(cdev) + CATPT_DRAM_##reg)
+
 #define catpt_readl_shim(cdev, reg) \
        readl(catpt_shim_addr(cdev) + CATPT_SHIM_##reg)
 #define catpt_writel_shim(cdev, reg, val) \