x86/microcode: Update the Intel processor flag scan check

The Family model check to read the processor flag MSR is misleading and
potentially incorrect. It doesn't consider Family while comparing the
model number. The original check did have a Family number but it got
lost/moved during refactoring.

intel_collect_cpu_info() is called through multiple paths such as early
initialization, CPU hotplug as well as IFS image load. Some of these
flows would be error prone due to the ambiguous check.

Correct the processor flag scan check to use a Family number and update
it to a VFM based one to make it more readable.

Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/r/20250219184133.816753-4-sohil.mehta@intel.com

diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index b657d78071c68e451877d61ea0a83ffd1592e462..f0e7ed012cfab8c2db9c0144c9f4e36302316346 100644 (file)
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -46,6 +46,7 @@
 #define INTEL_ANY                      IFM(X86_FAMILY_ANY, X86_MODEL_ANY)
 
 #define INTEL_PENTIUM_PRO              IFM(6, 0x01)
+#define INTEL_PENTIUM_III_DESCHUTES    IFM(6, 0x05)
 
 #define INTEL_CORE_YONAH               IFM(6, 0x0E)
 

diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index f3d534807d914a0234137e6446f870334f2b424b..819199bc0119b23fee8ae1ecd490d2fb6936dc4e 100644 (file)
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -74,7 +74,7 @@ void intel_collect_cpu_info(struct cpu_signature *sig)
        sig->pf = 0;
        sig->rev = intel_get_microcode_revision();
 
-       if (x86_model(sig->sig) >= 5 || x86_family(sig->sig) > 6) {
+       if (IFM(x86_family(sig->sig), x86_model(sig->sig)) >= INTEL_PENTIUM_III_DESCHUTES) {
                unsigned int val[2];
 
                /* get processor flags from MSR 0x17 */