phy: exynos5-usbdrd: convert some FIELD_PREP_CONST() to FIELD_PREP()

Use of FIELD_PREP_CONST() was a thinko - it's meant to be used for
(constant) initialisers, not constant values.

Use FIELD_PREP() where possible. It has better error checking and is
therefore the preferred macro to use in those cases.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240710-phy-field-prep-v1-1-2fa3f7dc4fc7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index df52b78a120b47d6d2517e4973534fb14a1de969..0cc5c4249447c95c6633d1b82b2685bfa7a34738 100644 (file)
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -607,7 +607,7 @@ exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready(struct exynos5_usbdrd_phy *phy_drd)
 
        reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL);
        reg &= ~SECPMACTL_PMA_REF_FREQ_SEL;
-       reg |= FIELD_PREP_CONST(SECPMACTL_PMA_REF_FREQ_SEL, 1);
+       reg |= FIELD_PREP(SECPMACTL_PMA_REF_FREQ_SEL, 1);
        /* SFR reset */
        reg |= (SECPMACTL_PMA_LOW_PWR | SECPMACTL_PMA_APB_SW_RST);
        reg &= ~(SECPMACTL_PMA_ROPLL_REF_CLK_SEL |
@@ -1123,19 +1123,19 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
        reg &= ~SSPPLLCTL_FSEL;
        switch (phy_drd->extrefclk) {
        case EXYNOS5_FSEL_50MHZ:
-               reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7);
+               reg |= FIELD_PREP(SSPPLLCTL_FSEL, 7);
                break;
        case EXYNOS5_FSEL_26MHZ:
-               reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6);
+               reg |= FIELD_PREP(SSPPLLCTL_FSEL, 6);
                break;
        case EXYNOS5_FSEL_24MHZ:
-               reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2);
+               reg |= FIELD_PREP(SSPPLLCTL_FSEL, 2);
                break;
        case EXYNOS5_FSEL_20MHZ:
-               reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1);
+               reg |= FIELD_PREP(SSPPLLCTL_FSEL, 1);
                break;
        case EXYNOS5_FSEL_19MHZ2:
-               reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0);
+               reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0);
                break;
        default:
                dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n",