Merge patch series "Support Multi-frequency scale for UFS"

Ziqi Chen <quic_ziqichen@quicinc.com> says:

With OPP V2 enabled, devfreq can scale clocks amongst multiple frequency
plans. However, the gear speed is only toggled between min and max during
clock scaling. Enable multi-level gear scaling by mapping clock frequencies
to gear speeds, so that when devfreq scales clock frequencies we can put
the UFS link at the appropraite gear speeds accordingly.

This series has been tested on below platforms -
sm8550 mtp + UFS3.1
SM8650 MTP + UFS3.1
SM8750 MTP + UFS4.0

Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Link: https://lore.kernel.org/r/20250213080008.2984807-1-quic_ziqichen@quicinc.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --cc Documentation/ABI/testing/sysfs-driver-ufs
index ab2adea56715d6af22b9e35da19c18a31929374c,da8d1437d3f4b5d3c5986d7bf2d0e8d953c1a5a0..ae0191295d29b8135bc6d5c41986bf41eebbd3be
--- 1/Documentation/ABI/testing/sysfs-driver-ufs
--- 2/Documentation/ABI/testing/sysfs-driver-ufs
+++ b/Documentation/ABI/testing/sysfs-driver-ufs
@@@ -1560,14 -1560,35 +1560,47 @@@ Description
                The Manufacturer ID is defined by JEDEC in JEDEC-JEP106.
                The file is read only.
  
 +What:         /sys/bus/platform/drivers/ufshcd/*/critical_health
 +What:         /sys/bus/platform/devices/*.ufs/critical_health
 +Date:         February 2025
 +Contact:      Avri Altman <avri.altman@wdc.com>
 +Description:  Report the number of times a critical health event has been
 +              reported by a UFS device. Further insight into the specific
 +              issue can be gained by reading one of: bPreEOLInfo,
 +              bDeviceLifeTimeEstA, bDeviceLifeTimeEstB,
 +              bWriteBoosterBufferLifeTimeEst, and bRPMBLifeTimeEst.
 +
 +              The file is read only.
++
+ What:         /sys/bus/platform/drivers/ufshcd/*/clkscale_enable
+ What:         /sys/bus/platform/devices/*.ufs/clkscale_enable
+ Date:         January 2025
+ Contact:      Ziqi Chen <quic_ziqichen@quicinc.com>
+ Description:
+               This attribute shows whether the UFS clock scaling is enabled or not.
+               And it can be used to enable/disable the clock scaling by writing
+               1 or 0 to this attribute.
+ 
+               The attribute is read/write.
+ 
+ What:         /sys/bus/platform/drivers/ufshcd/*/clkgate_enable
+ What:         /sys/bus/platform/devices/*.ufs/clkgate_enable
+ Date:         January 2025
+ Contact:      Ziqi Chen <quic_ziqichen@quicinc.com>
+ Description:
+               This attribute shows whether the UFS clock gating is enabled or not.
+               And it can be used to enable/disable the clock gating by writing
+               1 or 0 to this attribute.
+ 
+               The attribute is read/write.
+ 
+ What:         /sys/bus/platform/drivers/ufshcd/*/clkgate_delay_ms
+ What:         /sys/bus/platform/devices/*.ufs/clkgate_delay_ms
+ Date:         January 2025
+ Contact:      Ziqi Chen <quic_ziqichen@quicinc.com>
+ Description:
+               This attribute shows and sets the number of milliseconds of idle time
+               before the UFS driver starts to perform clock gating. This can
+               prevent the UFS from frequently performing clock gating/ungating.
+ 
+               The attribute is read/write.

diff --cc drivers/ufs/core/ufshcd-priv.h
Simple merge

diff --cc drivers/ufs/core/ufshcd.c
Simple merge

diff --cc drivers/ufs/host/ufs-mediatek.c
Simple merge

diff --cc drivers/ufs/host/ufs-qcom.c
index dee00f9a1281347cb853b1c8daf3cda588f9bff1,9e90d2ea23dea95a6168417119a49bc6a8edacb9..d03a07402223ba6bbbe609a5e85d071d7ad40bfa
--- 1/drivers/ufs/host/ufs-qcom.c
--- 2/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@@ -15,7 -15,7 +15,8 @@@
  #include <linux/platform_device.h>
  #include <linux/reset-controller.h>
  #include <linux/time.h>
 +#include <linux/unaligned.h>
+ #include <linux/units.h>
  
  #include <soc/qcom/ice.h>
  
@@@ -1369,11 -1348,14 +1371,11 @@@ static int ufs_qcom_set_core_clk_ctrl(s
        return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us);
  }
  
- static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
+ static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long freq)
  {
 -      struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 -      struct ufs_pa_layer_attr *attr = &host->dev_req_params;
        int ret;
  
 -      ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx,
 -                                attr->hs_rate, false, true);
 +      ret = ufs_qcom_cfg_timers(hba, true);
        if (ret) {
                dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__);
                return ret;

diff --cc include/ufs/ufshcd.h
Simple merge