perf/x86/intel/cstate: Add Nova Lake support

Similar to Lunar Lake and Panther Lake, Nova Lake supports CC1/CC6/CC7
and PC2/PC6/PC10 residency counters; it also adds support for MC6.

Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20251215182520.115822-2-zide.chen@intel.com

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index b719b0a68a2a1a2b2922b270b1295f4521160762..008f8ea5931592b9aa840268ca1707ed3ed8642f 100644 (file)
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -41,7 +41,7 @@
  *     MSR_CORE_C1_RES: CORE C1 Residency Counter
  *                      perf code: 0x00
  *                      Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
- *                                       MTL,SRF,GRR,ARL,LNL,PTL,WCL
+ *                                       MTL,SRF,GRR,ARL,LNL,PTL,WCL,NVL
  *                      Scope: Core (each processor core has a MSR)
  *     MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  *                            perf code: 0x01
@@ -53,19 +53,20 @@
  *                            Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
  *                                             SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
  *                                             TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- *                                             GRR,ARL,LNL,PTL,WCL
+ *                                             GRR,ARL,LNL,PTL,WCL,NVL
  *                            Scope: Core
  *     MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  *                            perf code: 0x03
  *                            Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
  *                                             ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
- *                                             PTL,WCL
+ *                                             PTL,WCL,NVL
  *                            Scope: Core
  *     MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
  *                            perf code: 0x00
  *                            Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
  *                                             KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
- *                                             RPL,SPR,MTL,ARL,LNL,SRF,PTL,WCL
+ *                                             RPL,SPR,MTL,ARL,LNL,SRF,PTL,WCL,
+ *                                             NVL
  *                            Scope: Package (physical package)
  *     MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
  *                            perf code: 0x01
@@ -78,7 +79,7 @@
  *                            Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
  *                                             SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
  *                                             TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- *                                             ARL,LNL,PTL,WCL
+ *                                             ARL,LNL,PTL,WCL,NVL
  *                            Scope: Package (physical package)
  *     MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
  *                            perf code: 0x03
@@ -98,11 +99,11 @@
  *                            perf code: 0x06
  *                            Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
  *                                             TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL,
- *                                             WCL
+ *                                             WCL,NVL
  *                            Scope: Package (physical package)
  *     MSR_MODULE_C6_RES_MS:  Module C6 Residency Counter.
  *                            perf code: 0x00
- *                            Available model: SRF,GRR
+ *                            Available model: SRF,GRR,NVL
  *                            Scope: A cluster of cores shared L2 cache
  *
  */
@@ -528,6 +529,18 @@ static const struct cstate_model lnl_cstates __initconst = {
                                  BIT(PERF_CSTATE_PKG_C10_RES),
 };
 
+static const struct cstate_model nvl_cstates __initconst = {
+       .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
+                                 BIT(PERF_CSTATE_CORE_C6_RES) |
+                                 BIT(PERF_CSTATE_CORE_C7_RES),
+
+       .module_events          = BIT(PERF_CSTATE_MODULE_C6_RES),
+
+       .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
+                                 BIT(PERF_CSTATE_PKG_C6_RES) |
+                                 BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
 static const struct cstate_model slm_cstates __initconst = {
        .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
                                  BIT(PERF_CSTATE_CORE_C6_RES),
@@ -656,6 +669,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
        X86_MATCH_VFM(INTEL_LUNARLAKE_M,        &lnl_cstates),
        X86_MATCH_VFM(INTEL_PANTHERLAKE_L,      &lnl_cstates),
        X86_MATCH_VFM(INTEL_WILDCATLAKE_L,      &lnl_cstates),
+       X86_MATCH_VFM(INTEL_NOVALAKE,           &nvl_cstates),
+       X86_MATCH_VFM(INTEL_NOVALAKE_L,         &nvl_cstates),
        { },
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);