(bfd *, char *, int *, const void *, int);
extern char *elfcore_write_aarch_mte
(bfd *, char *, int *, const void *, int);
+extern char *elfcore_write_aarch_morello
+ (bfd *, char *, int *, const void *, int);
extern char *elfcore_write_arc_v2
(bfd *, char *, int *, const void *, int);
extern char *elfcore_write_riscv_csr
note);
}
+static bool
+elfcore_grok_aarch_morello (bfd *abfd, Elf_Internal_Note *note)
+{
+ return elfcore_make_note_pseudosection (abfd, ".reg-aarch-morello", note);
+}
+
static bool
elfcore_grok_arc_v2 (bfd *abfd, Elf_Internal_Note *note)
{
else
return true;
+ case NT_ARM_MORELLO:
+ if (note->namesz == 6
+ && strcmp (note->namedata, "LINUX") == 0)
+ return elfcore_grok_aarch_morello (abfd, note);
+ else
+ return true;
+
case NT_PRPSINFO:
case NT_PSINFO:
if (bed->elf_backend_grok_psinfo)
size);
}
+char *
+elfcore_write_aarch_morello (bfd *abfd,
+ char *buf,
+ int *bufsiz,
+ const void *aarch_morello,
+ int size)
+{
+ char *note_name = "LINUX";
+ return elfcore_write_note (abfd, buf, bufsiz,
+ note_name, NT_ARM_MORELLO, aarch_morello, size);
+}
+
char *
elfcore_write_arc_v2 (bfd *abfd,
char *buf,
return elfcore_write_aarch_pauth (abfd, buf, bufsiz, data, size);
if (strcmp (section, ".reg-aarch-mte") == 0)
return elfcore_write_aarch_mte (abfd, buf, bufsiz, data, size);
+ if (strcmp (section, ".reg-aarch-morello") == 0)
+ return elfcore_write_aarch_morello (abfd, buf, bufsiz, data, size);
if (strcmp (section, ".reg-arc-v2") == 0)
return elfcore_write_arc_v2 (abfd, buf, bufsiz, data, size);
if (strcmp (section, ".gdb-tdesc") == 0)
placeholders so we can update the numbers later. */
static struct regcache_map_entry aarch64_linux_cregmap[] =
{
- /* FIXME-Morello: Need to decide if we are reading the whole 16 bytes or
- just the upper 8 bytes of the capability registers. */
- { 31, -1, 8 }, /* c0 ... c30 */
- { 1, -1, 8 }, /* Stack Pointer Capability */
- { 1, -1, 8 }, /* Program Counter Capability */
- { 1, -1, 16 }, /* Default Data Capability */
- { 1, -1, 8 },
+ { 31, -1, 16 }, /* c0 ... c30 */
+ { 1, -1, 16 }, /* pcc */
+ { 1, -1, 16 }, /* csp */
+ { 1, -1, 16 }, /* ddc */
+ { 1, -1, 16 }, /* ctpidr */
+ { 1, -1, 16 }, /* rcsp */
+ { 1, -1, 16 }, /* rddc */
+ { 1, -1, 16 }, /* rctpidr */
+ { 1, -1, 16 }, /* cid */
+ { 1, -1, 8 }, /* tag_map */
+ { 1, -1, 8 }, /* cctlr */
{ 0 }
};
"TLS register", cb_data);
}
- /* FIXME-Morello: We still need to provide a valid check for the presence of
- capability registers. */
+ /* Morello capability registers. */
if (tdep->has_capability ())
{
- cb (".reg-cap", AARCH64_LINUX_CREGS_SIZE,
+ cb (".reg-aarch-morello", AARCH64_LINUX_CREGS_SIZE,
AARCH64_LINUX_CREGS_SIZE, &aarch64_linux_cregset,
NULL, cb_data);
}
if (tdep->has_capability ())
{
- /* Initialize the register numbers for the core file register set. */
- /* FIXME-Morello: This needs to be updated. */
+ /* Initialize the register numbers for the core file register set.
+ Please note the PCC/CSP position in GDB's target description is
+ the inverse of the position in the Linux Kernel's user_morello_state
+ data structure. This can cause some confusion. */
aarch64_linux_cregmap[0].regno = tdep->cap_reg_base;
- aarch64_linux_cregmap[1].regno = tdep->cap_reg_base + 32;
- aarch64_linux_cregmap[2].regno = tdep->cap_reg_base + 31;
- aarch64_linux_cregmap[3].regno = tdep->cap_reg_base + 33;
+ aarch64_linux_cregmap[1].regno = tdep->cap_reg_pcc;
+ aarch64_linux_cregmap[2].regno = tdep->cap_reg_csp;
+
+ /* Set the rest of the registers. */
+ int next_regnum = tdep->cap_reg_base + 33;
+ for (int i = 3; i <= 10; i++)
+ {
+ aarch64_linux_cregmap[i].regno = next_regnum;
+ next_regnum++;
+ }
set_gdbarch_report_signal_info (gdbarch,
aarch64_linux_report_signal_info);