KVM: arm64: Use computed masks as sanitisers for FGT registers

Now that we have computed RES0 bits, use them to sanitise the
guest view of FGT registers.

Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index 16f6129c70b59dc4148168e866a0937554dbb8b0..479ffd25eea63e8f4df2d326c16916ef6554a795 100644 (file)
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -1137,8 +1137,8 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
                res0 |= HFGRTR_EL2_nS2POR_EL1;
        if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, AIE, IMP))
                res0 |= (HFGRTR_EL2_nMAIR2_EL1 | HFGRTR_EL2_nAMAIR2_EL1);
-       set_sysreg_masks(kvm, HFGRTR_EL2, res0 | __HFGRTR_EL2_RES0, res1);
-       set_sysreg_masks(kvm, HFGWTR_EL2, res0 | __HFGWTR_EL2_RES0, res1);
+       set_sysreg_masks(kvm, HFGRTR_EL2, res0 | hfgrtr_masks.res0, res1);
+       set_sysreg_masks(kvm, HFGWTR_EL2, res0 | hfgwtr_masks.res0, res1);
 
        /* HDFG[RW]TR_EL2 */
        res0 = res1 = 0;
@@ -1176,7 +1176,7 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
                         HDFGRTR_EL2_nBRBDATA);
        if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P2))
                res0 |= HDFGRTR_EL2_nPMSNEVFR_EL1;
-       set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | HDFGRTR_EL2_RES0, res1);
+       set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | hdfgrtr_masks.res0, res1);
 
        /* Reuse the bits from the read-side and add the write-specific stuff */
        if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP))
@@ -1185,10 +1185,10 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
                res0 |= HDFGWTR_EL2_TRCOSLAR;
        if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceFilt, IMP))
                res0 |= HDFGWTR_EL2_TRFCR_EL1;
-       set_sysreg_masks(kvm, HFGWTR_EL2, res0 | HDFGWTR_EL2_RES0, res1);
+       set_sysreg_masks(kvm, HFGWTR_EL2, res0 | hdfgwtr_masks.res0, res1);
 
        /* HFGITR_EL2 */
-       res0 = HFGITR_EL2_RES0;
+       res0 = hfgitr_masks.res0;
        res1 = HFGITR_EL2_RES1;
        if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, DPB, DPB2))
                res0 |= HFGITR_EL2_DCCVADP;
@@ -1222,7 +1222,7 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
        set_sysreg_masks(kvm, HFGITR_EL2, res0, res1);
 
        /* HAFGRTR_EL2 - not a lot to see here */
-       res0 = HAFGRTR_EL2_RES0;
+       res0 = hafgrtr_masks.res0;
        res1 = HAFGRTR_EL2_RES1;
        if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, V1P1))
                res0 |= ~(res0 | res1);