RISC-V: Fix indexed store output template [PR123780].

This one slipped through when bulk-changing the gather/scatter patterns.

Regtested on rv64gcv_zvl512b.  Going to commit as obvious.

	PR target/123780

gcc/ChangeLog:

	* config/riscv/vector.md: Correct output template.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr123780.c: New test.

Signed-off-by: Robin Dapp <rdapp@oss.qualcomm.com>

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 6bf01338117c9ddb1b13c2469747d0360c530264..18d9c2b3346b3203bf239627bf300d00ca4e0438 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -2746,7 +2746,7 @@
           (match_operand:<VINDEX_OCT_TRUNC> 2 "register_operand" "  vr")
           (match_operand:VEEWEXT8 3 "register_operand"  "  vr")] ORDER))]
   "TARGET_VECTOR"
-  "vs<order>xei<quad_trunc_sew>.v\t%3,(%z1),%2%p0"
+  "vs<order>xei<oct_trunc_sew>.v\t%3,(%z1),%2%p0"
   [(set_attr "type" "vst<order>x")
    (set_attr "mode" "<MODE>")])
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr123780.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr123780.c
new file mode 100644 (file)
index 0000000..7bf3eb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr123780.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O1" } */
+
+#include <riscv_vector.h>
+
+double k[30], l[30];
+
+int main () {
+  for (int i = 0; i < 30; ++i) { k[i] = 1; }
+
+  for (size_t m = 0, avl = 30; avl > 0;) {
+    size_t s = __riscv_vsetvl_e8mf8(avl);
+    vfloat64m1_t q = __riscv_vle64_v_f64m1(&k[m], s);
+    q = __riscv_vfneg_v_f64m1(q, s);
+    vuint8mf8_t r = __riscv_vsll_vx_u8mf8(__riscv_vid_v_u8mf8(s), 3, s);
+    __riscv_vsoxei8(&l[m], r, q, s);
+    avl -= s; m += s;
+  }
+}
+
+/* { dg-final { scan-assembler-times "vsoxei8" 1 } } */