In some obscure circumstances, the allocator would incorrectly omit a

spill store on the basis that the register being spilled had the same
value as the spill slot being written to.  This change is believed to
make the equals-spill-slot optimisation correct.  Fixes a bug first
observed by Nuno Lopes and later by Marc-Oliver Straub.

git-svn-id: svn://svn.valgrind.org/vex/trunk@1853

diff --git a/VEX/priv/host-generic/reg_alloc2.c b/VEX/priv/host-generic/reg_alloc2.c
index c64333daac3836567b3d1f5a77642f1b3d907928..e57d38c7e2562d2b31074054e0502d9993c00d08 100644 (file)
--- a/VEX/priv/host-generic/reg_alloc2.c
+++ b/VEX/priv/host-generic/reg_alloc2.c
@@ -1335,7 +1335,15 @@ HInstrArray* doRegisterAllocation (
                EMIT_INSTR( (*genReload)( rreg_state[k].rreg,
                                          vreg_lrs[m].spill_offset,
                                          mode64 ) );
-               rreg_state[k].eq_spill_slot = True;
+               /* This rreg is read or modified by the instruction.
+                  If it's merely read we can claim it now equals the
+                  spill slot, but not so if it is modified. */
+               if (reg_usage.mode[j] == HRmRead) {
+                  rreg_state[k].eq_spill_slot = True;
+               } else {
+                  vassert(reg_usage.mode[j] == HRmModify);
+                  rreg_state[k].eq_spill_slot = False;
+               }
             } else {
                rreg_state[k].eq_spill_slot = False;
             }
@@ -1424,11 +1432,19 @@ HInstrArray* doRegisterAllocation (
             EMIT_INSTR( (*genReload)( rreg_state[spillee].rreg,
                                       vreg_lrs[m].spill_offset,
                                       mode64 ) );
-            rreg_state[spillee].eq_spill_slot = True;
+            /* This rreg is read or modified by the instruction.
+               If it's merely read we can claim it now equals the
+               spill slot, but not so if it is modified. */
+            if (reg_usage.mode[j] == HRmRead) {
+               rreg_state[spillee].eq_spill_slot = True;
+            } else {
+               vassert(reg_usage.mode[j] == HRmModify);
+               rreg_state[spillee].eq_spill_slot = False;
+            }
          }
 
          /* So after much twisting and turning, we have vreg mapped to
-            rreg_state[furthest_k].rreg.  Note that in the map. */
+            rreg_state[spillee].rreg.  Note that in the map. */
          addToHRegRemap(&remap, vreg, rreg_state[spillee].rreg);
 
       } /* iterate over registers in this instruction. */