/* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
/* EXTRA_EXTENSION_FLAGS */ 0)
+DEFINE_RISCV_EXT(
+ /* NAME */ smcntrpmf,
+ /* UPPERCAE_NAME */ SMCNTRPMF,
+ /* FULL_NAME */ "Cycle and instret privilege mode filtering",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"zicsr"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ sm,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
DEFINE_RISCV_EXT(
/* NAME */ smepmp,
/* UPPERCAE_NAME */ SMEPMP,
Mask(SMAIA) Var(riscv_sm_subext)
+Mask(SMCNTRPMF) Var(riscv_sm_subext)
+
Mask(SMEPMP) Var(riscv_sm_subext)
Mask(SMMPM) Var(riscv_sm_subext)
@tab 1.0
@tab Advanced interrupt architecture extension
+@item smcntrpmf
+@tab 1.0
+@tab Cycle and instret privilege mode filtering
+
@item smepmp
@tab 1.0
@tab PMP Enhancements for memory access and execution prevention on Machine mode