irqchip/ocelot: Comment sticky register clearing code

Add comment to the sticky register clearing code.

Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20240925184416.54204-3-matsievskiysv@gmail.com

diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index c19ab379e8c5ea85f387cb0ce754c4c057fdaee7..3dc745b14cafaceaf40b44d6aef61a995c7637aa 100644 (file)
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -84,6 +84,12 @@ static void ocelot_irq_unmask(struct irq_data *data)
        u32 val;
 
        irq_gc_lock(gc);
+       /*
+        * Clear sticky bits for edge mode interrupts.
+        * Serval has only one trigger register replication, but the adjacent
+        * register is always read as zero, so there's no need to handle this
+        * case separately.
+        */
        val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |
                irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));
        if (!(val & mask))