riscv: Fix scope for memory model calculation

During libgcc configure stage for riscv32-none-elf, when
"--enable-checking=yes,rtl" has been activated, the following error
is observed:

  during RTL pass: final
  conftest.c: In function 'main':
  conftest.c:16:1: internal compiler error: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4462
     16 | }
        | ^
  0x843c4d rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*)
          /mnt/nvme/dinux/local-workspace/gcc/gcc/rtl.cc:916
  0x8ea823 riscv_print_operand
          /mnt/nvme/dinux/local-workspace/gcc/gcc/config/riscv/riscv.cc:4462
  0xde84b5 output_operand(rtx_def*, int)
          /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3632
  0xde8ef8 output_asm_insn(char const*, rtx_def**)
          /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3544
  0xded33b output_asm_insn(char const*, rtx_def**)
          /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3421
  0xded33b final_scan_insn_1
          /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2841
  0xded6cb final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
          /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2887
  0xded8b7 final_1
          /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:1979
  0xdee518 rest_of_handle_final
          /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4240
  0xdee518 execute
          /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4318

Fix by moving the calculation of memmodel to the cases where it is used.

Regression tested for riscv32-none-elf. No changes in gcc.sum and
g++.sum.

	PR target/109725

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_print_operand): Calculate
	memmodel only when it is valid.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4ff3758434cbb3ef108e6e813c295306f652dc6e..60ebd9903e53c3ebe0c4b6b22d88ef29950372f6 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4459,7 +4459,6 @@ riscv_print_operand (FILE *file, rtx op, int letter)
     }
   machine_mode mode = GET_MODE (op);
   enum rtx_code code = GET_CODE (op);
-  const enum memmodel model = memmodel_base (INTVAL (op));
 
   switch (letter)
     {
@@ -4596,7 +4595,8 @@ riscv_print_operand (FILE *file, rtx op, int letter)
       fputs (GET_RTX_NAME (code), file);
       break;
 
-    case 'A':
+    case 'A': {
+      const enum memmodel model = memmodel_base (INTVAL (op));
       if (riscv_memmodel_needs_amo_acquire (model)
          && riscv_memmodel_needs_amo_release (model))
        fputs (".aqrl", file);
@@ -4605,18 +4605,23 @@ riscv_print_operand (FILE *file, rtx op, int letter)
       else if (riscv_memmodel_needs_amo_release (model))
        fputs (".rl", file);
       break;
+    }
 
-    case 'I':
+    case 'I': {
+      const enum memmodel model = memmodel_base (INTVAL (op));
       if (model == MEMMODEL_SEQ_CST)
        fputs (".aqrl", file);
       else if (riscv_memmodel_needs_amo_acquire (model))
        fputs (".aq", file);
       break;
+    }
 
-    case 'J':
+    case 'J': {
+      const enum memmodel model = memmodel_base (INTVAL (op));
       if (riscv_memmodel_needs_amo_release (model))
        fputs (".rl", file);
       break;
+    }
 
     case 'i':
       if (code != REG)