counter: stm32-timer-cnt: Add check for clk_enable()

[ Upstream commit 842c3755a6bfbfcafa4a1438078d2485a9eb1d87 ]

Add check for the return value of clk_enable() in order to catch the
potential exception.

Fixes: c5b8425514da ("counter: stm32-timer-cnt: add power management support")
Fixes: ad29937e206f ("counter: Add STM32 Timer quadrature encoder")
Signed-off-by: Jiasheng Jiang <jiashengjiangcool@gmail.com>
Link: https://lore.kernel.org/r/20241104191825.40155-1-jiashengjiangcool@gmail.com
Signed-off-by: William Breathitt Gray <wbg@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c
index 186e73d6ccb455d57c70566a281c62d5299ebe0f..9c188d9edd89ffcf5a9926248fe03b0fb56ae61e 100644 (file)
--- a/drivers/counter/stm32-timer-cnt.c
+++ b/drivers/counter/stm32-timer-cnt.c
@@ -214,11 +214,17 @@ static int stm32_count_enable_write(struct counter_device *counter,
 {
        struct stm32_timer_cnt *const priv = counter_priv(counter);
        u32 cr1;
+       int ret;
 
        if (enable) {
                regmap_read(priv->regmap, TIM_CR1, &cr1);
-               if (!(cr1 & TIM_CR1_CEN))
-                       clk_enable(priv->clk);
+               if (!(cr1 & TIM_CR1_CEN)) {
+                       ret = clk_enable(priv->clk);
+                       if (ret) {
+                               dev_err(counter->parent, "Cannot enable clock %d\n", ret);
+                               return ret;
+                       }
+               }
 
                regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
                                   TIM_CR1_CEN);
@@ -816,7 +822,11 @@ static int __maybe_unused stm32_timer_cnt_resume(struct device *dev)
                return ret;
 
        if (priv->enabled) {
-               clk_enable(priv->clk);
+               ret = clk_enable(priv->clk);
+               if (ret) {
+                       dev_err(dev, "Cannot enable clock %d\n", ret);
+                       return ret;
+               }
 
                /* Restore registers that may have been lost */
                regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);