rs6000: Rename instruction xvcvbf16sp to xvcvbf16spn

The xvcvbf16sp mnemonic, which was just added in ISA 3.1 has been renamed
to xvcvbf16spn, to make it consistent with the other non-signaling conversion
instructions which all end with "n".  The only use of this instruction is in
an MMA conversion built-in function, so there is little to no compatibility
issue.

2020-08-18  Peter Bergner  <bergner@linux.ibm.com>

gcc/
	* config/rs6000/rs6000-builtin.def (BU_VSX_1): Rename xvcvbf16sp to
	xvcvbf16spn.
	* config/rs6000/rs6000-call.c (builtin_function_type): Likewise.
	* config/rs6000/vsx.md: Likewise.
	* doc/extend.texi: Likewise.

gcc/testsuite/
	* gcc.target/powerpc/mma-builtin-3.c: Rename xvcvbf16sp to xvcvbf16spn.

(cherry picked from commit 94bedeaf694c728607a718d599edb4d74a2813c0)

diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index b9eef87f1d34fbd3e2f11b6ce4aa633402f6d4b7..88f78cb0a159002dd8a185463d966bd6ff6f730d 100644 (file)
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -2698,7 +2698,7 @@ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
              RS6000_BTC_MISC)
 
 /* POWER10 MMA builtins.  */
-BU_VSX_1 (XVCVBF16SP,      "xvcvbf16sp",       MISC, vsx_xvcvbf16sp)
+BU_VSX_1 (XVCVBF16SPN,     "xvcvbf16spn",      MISC, vsx_xvcvbf16spn)
 BU_VSX_1 (XVCVSPBF16,      "xvcvspbf16",       MISC, vsx_xvcvspbf16)
 
 BU_MMA_1 (XXMFACC,         "xxmfacc",          QUAD, mma_xxmfacc)

diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 1b29eadd131527270a77cd582a244d073fc9ff65..2cf78dfa5fe99a0a994f92883fbbd541f8d2af87 100644 (file)
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -13384,7 +13384,7 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
     case MISC_BUILTIN_CDTBCD:
     case MISC_BUILTIN_CBCDTD:
     case VSX_BUILTIN_XVCVSPBF16:
-    case VSX_BUILTIN_XVCVBF16SP:
+    case VSX_BUILTIN_XVCVBF16SPN:
       h.uns_p[0] = 1;
       h.uns_p[1] = 1;
       break;

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c0309196ba42b87547e43fb568070480d621f116..bf6e22b65d9ad482818c68e0379b83573cd7ef2c 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -295,7 +295,7 @@
    UNSPEC_VSX_DIVUD
    UNSPEC_VSX_MULSD
    UNSPEC_VSX_SIGN_EXTEND
-   UNSPEC_VSX_XVCVBF16SP
+   UNSPEC_VSX_XVCVBF16SPN
    UNSPEC_VSX_XVCVSPBF16
    UNSPEC_VSX_XVCVSPSXDS
    UNSPEC_VSX_XVCVSPHP
@@ -348,10 +348,10 @@
   ])
 
 (define_int_iterator XVCVBF16  [UNSPEC_VSX_XVCVSPBF16
-                                UNSPEC_VSX_XVCVBF16SP])
+                                UNSPEC_VSX_XVCVBF16SPN])
 
 (define_int_attr xvcvbf16       [(UNSPEC_VSX_XVCVSPBF16 "xvcvspbf16")
-                                (UNSPEC_VSX_XVCVBF16SP "xvcvbf16sp")])
+                                (UNSPEC_VSX_XVCVBF16SPN "xvcvbf16spn")])
 
 ;; VSX moves
 

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 7dce127b5d3523445cc217680d73d5d332a82264..25fa3d549a0eb6ab372c18ec1499bbbb740286b6 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -20959,7 +20959,7 @@ void __builtin_mma_assemble_pair (__vector_pair *, vec_t, vec_t);
 void __builtin_mma_disassemble_pair (void *, __vector_pair *);
 
 vec_t __builtin_vsx_xvcvspbf16 (vec_t);
-vec_t __builtin_vsx_xvcvbf16sp (vec_t);
+vec_t __builtin_vsx_xvcvbf16spn (vec_t);
 @end smallexample
 
 @node RX Built-in Functions

diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c
index 29eb275499906d496dee65a3078b0ac82cbc82f3..9bec78d333fb679aa14f0a32b6433c96bf6d0e37 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c
@@ -18,7 +18,7 @@ void
 foo1 (vec_t *vec)
 {
   vec[1] = __builtin_vsx_xvcvspbf16 (vec[0]);
-  vec[3] = __builtin_vsx_xvcvbf16sp (vec[2]);
+  vec[3] = __builtin_vsx_xvcvbf16spn (vec[2]);
 }
 
 /* { dg-final { scan-assembler-times {\mxxmtacc\M} 1 } } */
@@ -28,4 +28,4 @@ foo1 (vec_t *vec)
 /* { dg-final { scan-assembler-not {\mlxvp\M} } } */
 /* { dg-final { scan-assembler-not {\mstxvp\M} } } */
 /* { dg-final { scan-assembler-times {\mxvcvspbf16\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvcvbf16sp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvcvbf16spn\M} 1 } } */