{
int ret, i;
- reg += CS35L56_SDW_ADDR_OFFSET;
-
for (i = 0; i < val_size; i += sizeof(u32)) {
/* Poll for bus bridge idle */
ret = cs35l56_sdw_poll_mem_status(peripheral,
reg = le32_to_cpu(*(const __le32 *)reg_buf);
- if (cs35l56_is_otp_register(reg))
+ if (cs35l56_is_otp_register(reg - CS35L56_SDW_ADDR_OFFSET))
return cs35l56_sdw_slow_read(peripheral, reg, buf8, val_size);
- reg += CS35L56_SDW_ADDR_OFFSET;
-
if (val_size == 4)
return cs35l56_sdw_read_one(peripheral, reg, val_buf);
int ret;
reg = le32_to_cpu(*(const __le32 *)reg_buf);
- reg += CS35L56_SDW_ADDR_OFFSET;
if (val_size == 4)
return cs35l56_sdw_write_one(peripheral, reg, src_be);
const struct regmap_config cs35l56_regmap_sdw = {
.reg_bits = 32,
+ .reg_base = 0x8000,
.val_bits = 32,
.reg_stride = 4,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
+ .reg_base = 0x8000,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L56_DSP1_PMEM_5114,