re PR target/49965 (libgomp.c++/reduction-4.C and libgomp.c++/task-8.C FAIL on Solari...

	PR target/49965
	* config/sparc/sparc.md (mov<I:mode>cc): Do not save comparison code.
	(mov<F:mode>cc): Likewise.

From-SVN: r179829

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ae99530c412646e9d5e6c452d58107fc46ae7518..51c7312600dab42087aa2f0c77f20e92ddf2fae3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2011-10-11  Eric Botcazou  <ebotcazou@adacore.com>
+
+       PR target/49965
+       * config/sparc/sparc.md (mov<I:mode>cc): Do not save comparison code.
+       (mov<F:mode>cc): Likewise.
+
 2011-10-11  Janis Johnson  <janisjo@codesourcery.com>
 
        PR c++/44473

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 97b58b0a9678da8a08918efe0be4889ee56d0d2b..a55a56a9397b2f141a26f3d1f9f123e30619c92a 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2477,11 +2477,9 @@
                        (match_operand:I 3 "arith10_operand" "")))]
   "TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)"
 {
-  enum rtx_code code = GET_CODE (operands[1]);
   rtx cc_reg;
 
-  if (GET_MODE (XEXP (operands[1], 0)) == DImode
-      && ! TARGET_ARCH64)
+  if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64)
     FAIL;
 
   if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD)
@@ -2492,12 +2490,14 @@
   if (XEXP (operands[1], 1) == const0_rtx
       && GET_CODE (XEXP (operands[1], 0)) == REG
       && GET_MODE (XEXP (operands[1], 0)) == DImode
-      && v9_regcmp_p (code))
+      && v9_regcmp_p (GET_CODE (operands[1])))
     cc_reg = XEXP (operands[1], 0);
   else
     cc_reg = gen_compare_reg (operands[1]);
 
-  operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
+  operands[1]
+    = gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg,
+                     const0_rtx);
 })
 
 (define_expand "mov<F:mode>cc"
@@ -2507,11 +2507,9 @@
                        (match_operand:F 3 "register_operand" "")))]
   "TARGET_V9 && TARGET_FPU"
 {
-  enum rtx_code code = GET_CODE (operands[1]);
   rtx cc_reg;
 
-  if (GET_MODE (XEXP (operands[1], 0)) == DImode
-      && ! TARGET_ARCH64)
+  if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64)
     FAIL;
 
   if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD)
@@ -2522,12 +2520,14 @@
   if (XEXP (operands[1], 1) == const0_rtx
       && GET_CODE (XEXP (operands[1], 0)) == REG
       && GET_MODE (XEXP (operands[1], 0)) == DImode
-      && v9_regcmp_p (code))
+      && v9_regcmp_p (GET_CODE (operands[1])))
     cc_reg = XEXP (operands[1], 0);
   else
     cc_reg = gen_compare_reg (operands[1]);
 
-  operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
+  operands[1]
+    = gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg,
+                     const0_rtx);
 })
 
 ;; Conditional move define_insns