static struct qcom_nand_controller *
get_qcom_nand_controller(struct nand_chip *chip)
{
- return (struct qcom_nand_controller *)
- ((u8 *)chip->controller - sizeof(struct qcom_nand_controller));
+ return container_of(chip->controller, struct qcom_nand_controller,
+ controller);
}
static u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
{
u32 nand_ctrl;
- nand_controller_init(nandc->controller);
- nandc->controller->ops = &qcom_nandc_ops;
+ nand_controller_init(&nandc->controller);
+ nandc->controller.ops = &qcom_nandc_ops;
/* kill onenand */
if (!nandc->props->nandc_part_of_qpic)
chip->legacy.block_bad = qcom_nandc_block_bad;
chip->legacy.block_markbad = qcom_nandc_block_markbad;
- chip->controller = nandc->controller;
+ chip->controller = &nandc->controller;
chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA |
NAND_SKIP_BBTSCAN;
static int qcom_nandc_probe(struct platform_device *pdev)
{
struct qcom_nand_controller *nandc;
- struct nand_controller *controller;
const void *dev_data;
struct device *dev = &pdev->dev;
struct resource *res;
int ret;
- nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc) + sizeof(*controller),
- GFP_KERNEL);
+ nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
if (!nandc)
return -ENOMEM;
- controller = (struct nand_controller *)&nandc[1];
platform_set_drvdata(pdev, nandc);
nandc->dev = dev;
- nandc->controller = controller;
dev_data = of_device_get_match_data(dev);
if (!dev_data) {
#ifndef __MTD_NAND_QPIC_COMMON_H__
#define __MTD_NAND_QPIC_COMMON_H__
+#include <linux/mtd/rawnand.h>
+
/* NANDc reg offsets */
#define NAND_FLASH_CMD 0x00
#define NAND_ADDR0 0x04
const struct qcom_nandc_props *props;
- struct nand_controller *controller;
+ struct nand_controller controller;
struct qpic_spi_nand *qspi;
struct list_head host_list;