re PR target/41900 (call *%esp shouldn't be generated because of CPU errata)

	PR target/41900
	* config/i386/i386.h (ix86_arch_indices) <X86_ARCH_CALL_ESP>: New.
	(TARGET_CALL_ESP): New define.
	* config/i386/i386.c (initial_ix86_tune_features): Initialize
	X86_ARCH_CALL_ESP.
	* config/i386/i386.md (*call_pop_1_esp, *call_1_esp,
	*call_value_pop_1_esp, *call_value_1_esp): Rename from *call_pop_1,
	*call_1, *call_value_pop_1 and *call_value_1.  Depend on
	TARGET_CALL_ESP.
	(*call_pop_1, *call_1, *call_value_pop_1, *call_value_1):
	New patterns, use "lsm" as operand 1 constraint.
	* config/i386/predicates.md (call_insn_operand): Depend on
	index_register_operand for !TARGET_CALL_ESP to avoid %esp register.

testsuite/ChangeLog:

	PR target/41900
	* gcc.target/i386/pr41900.c: New test.

From-SVN: r153932

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e32dbd38d0cd14992d30da78d9c697562cccf3d4..716621905841ee2f0862640dad88542cd72005bd 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2009-11-05  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/41900
+       * config/i386/i386.h (ix86_arch_indices) <X86_ARCH_CALL_ESP>: New.
+       (TARGET_CALL_ESP): New define.
+       * config/i386/i386.c (initial_ix86_tune_features): Initialize
+       X86_ARCH_CALL_ESP.
+       * config/i386/i386.md (*call_pop_1_esp, *call_1_esp,
+       *call_value_pop_1_esp, *call_value_1_esp): Rename from *call_pop_1,
+       *call_1, *call_value_pop_1 and *call_value_1.  Depend on
+       TARGET_CALL_ESP.
+       (*call_pop_1, *call_1, *call_value_pop_1, *call_value_1):
+       New patterns, use "lsm" as operand 1 constraint.
+       * config/i386/predicates.md (call_insn_operand): Depend on
+       index_register_operand for !TARGET_CALL_ESP to avoid %esp register.
+
 2009-10-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
        Backport from mainline:
@@ -10,7 +26,7 @@
 
 2009-10-20  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
-        Backport from mainline:
+       Backport from mainline:
        2009-10-15  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
        PR target/41702

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d9f9b8cd3e440c549601123da37b3bfc0cd1ac4a..97d77d396eebb1d8906376defa676e20d859389e 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1451,6 +1451,11 @@ unsigned int ix86_arch_features[X86_ARCH_LAST] = {
 
   /* X86_ARCH_BSWAP: Byteswap was added for 80486.  */
   ~m_386,
+
+  /* X86_ARCH_CALL_ESP: P6 processors will jump to the address after
+     the decrement (so they will execute return address as code).  See
+     Pentium Pro errata 70, Pentium 2 errata A33, Pentium 3 errata E17.  */
+  ~(m_386 | m_486 | m_PENT | m_PPRO),
 };
 
 static const unsigned int x86_accumulate_outgoing_args

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 1d76c467b95d1ecd406e1018a41964080e1230b8..849226d7b511b2f6de0a3e5352270fa652a33541 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -372,6 +372,7 @@ enum ix86_arch_indices {
   X86_ARCH_CMPXCHG8B,
   X86_ARCH_XADD,
   X86_ARCH_BSWAP,
+  X86_ARCH_CALL_ESP,
 
   X86_ARCH_LAST
 };
@@ -383,6 +384,7 @@ extern unsigned int ix86_arch_features[X86_ARCH_LAST];
 #define TARGET_CMPXCHG8B       ix86_arch_features[X86_ARCH_CMPXCHG8B]
 #define TARGET_XADD            ix86_arch_features[X86_ARCH_XADD]
 #define TARGET_BSWAP           ix86_arch_features[X86_ARCH_BSWAP]
+#define TARGET_CALL_ESP                ix86_arch_features[X86_ARCH_CALL_ESP]
 
 #define TARGET_FISTTP          (TARGET_SSE3 && TARGET_80387)
 

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2c6b3a3d3c5ae1a336aec37f51cbe1721891bbd4..59ba88528aea4fc276442d5d8682b84bfd2abf7d 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -14682,12 +14682,25 @@
 }
   [(set_attr "type" "call")])
 
-(define_insn "*call_pop_1"
+(define_insn "*call_pop_1_esp"
   [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
         (match_operand:SI 1 "" ""))
    (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
                            (match_operand:SI 2 "immediate_operand" "i")))]
-  "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+{
+  if (constant_call_address_operand (operands[0], Pmode))
+    return "call\t%P0";
+  return "call\t%A0";
+}
+  [(set_attr "type" "call")])
+
+(define_insn "*call_pop_1"
+  [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm"))
+        (match_operand:SI 1 "" ""))
+   (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+                           (match_operand:SI 2 "immediate_operand" "i")))]
+  "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
 {
   if (constant_call_address_operand (operands[0], Pmode))
     return "call\t%P0";
@@ -14700,7 +14713,7 @@
         (match_operand:SI 1 "" ""))
    (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
                            (match_operand:SI 2 "immediate_operand" "i,i,i,i")))]
-  "SIBLING_CALL_P (insn) && !TARGET_64BIT"
+  "!TARGET_64BIT && SIBLING_CALL_P (insn)"
 {
   if (constant_call_address_operand (operands[0], Pmode))
     return "jmp\t%P0";
@@ -14740,10 +14753,21 @@
 }
   [(set_attr "type" "call")])
 
-(define_insn "*call_1"
+(define_insn "*call_1_esp"
   [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
         (match_operand 1 "" ""))]
-  "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+{
+  if (constant_call_address_operand (operands[0], Pmode))
+    return "call\t%P0";
+  return "call\t%A0";
+}
+  [(set_attr "type" "call")])
+
+(define_insn "*call_1"
+  [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm"))
+        (match_operand 1 "" ""))]
+  "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
 {
   if (constant_call_address_operand (operands[0], Pmode))
     return "call\t%P0";
@@ -14754,7 +14778,7 @@
 (define_insn "*sibcall_1"
   [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
         (match_operand 1 "" ""))]
-  "SIBLING_CALL_P (insn) && !TARGET_64BIT"
+  "!TARGET_64BIT && SIBLING_CALL_P (insn)"
 {
   if (constant_call_address_operand (operands[0], Pmode))
     return "jmp\t%P0";
@@ -14765,7 +14789,7 @@
 (define_insn "*call_1_rex64"
   [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
         (match_operand 1 "" ""))]
-  "!SIBLING_CALL_P (insn) && TARGET_64BIT
+  "TARGET_64BIT && !SIBLING_CALL_P (insn)
    && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC"
 {
   if (constant_call_address_operand (operands[0], Pmode))
@@ -14777,21 +14801,21 @@
 (define_insn "*call_1_rex64_large"
   [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rm"))
         (match_operand 1 "" ""))]
-  "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+  "TARGET_64BIT && !SIBLING_CALL_P (insn)"
   "call\t%A0"
   [(set_attr "type" "call")])
 
 (define_insn "*sibcall_1_rex64"
   [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
         (match_operand 1 "" ""))]
-  "SIBLING_CALL_P (insn) && TARGET_64BIT"
+  "TARGET_64BIT && SIBLING_CALL_P (insn)"
   "jmp\t%P0"
   [(set_attr "type" "call")])
 
 (define_insn "*sibcall_1_rex64_v"
   [(call (mem:QI (reg:DI R11_REG))
         (match_operand 0 "" ""))]
-  "SIBLING_CALL_P (insn) && TARGET_64BIT"
+  "TARGET_64BIT && SIBLING_CALL_P (insn)"
   "jmp\t{*%%}r11"
   [(set_attr "type" "call")])
 
@@ -21063,13 +21087,27 @@
 }
   [(set_attr "type" "callv")])
 
-(define_insn "*call_value_pop_1"
+(define_insn "*call_value_pop_1_esp"
   [(set (match_operand 0 "" "")
        (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
              (match_operand:SI 2 "" "")))
    (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
                            (match_operand:SI 3 "immediate_operand" "i")))]
-  "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+{
+  if (constant_call_address_operand (operands[1], Pmode))
+    return "call\t%P1";
+  return "call\t%A1";
+}
+  [(set_attr "type" "callv")])
+
+(define_insn "*call_value_pop_1"
+  [(set (match_operand 0 "" "")
+       (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm"))
+             (match_operand:SI 2 "" "")))
+   (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+                           (match_operand:SI 3 "immediate_operand" "i")))]
+  "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
 {
   if (constant_call_address_operand (operands[1], Pmode))
     return "call\t%P1";
@@ -21117,11 +21155,23 @@
 }
   [(set_attr "type" "callv")])
 
-(define_insn "*call_value_1"
+(define_insn "*call_value_1_esp"
   [(set (match_operand 0 "" "")
        (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
              (match_operand:SI 2 "" "")))]
-  "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+{
+  if (constant_call_address_operand (operands[1], Pmode))
+    return "call\t%P1";
+  return "call\t%A1";
+}
+  [(set_attr "type" "callv")])
+
+(define_insn "*call_value_1"
+  [(set (match_operand 0 "" "")
+       (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm"))
+             (match_operand:SI 2 "" "")))]
+  "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
 {
   if (constant_call_address_operand (operands[1], Pmode))
     return "call\t%P1";
@@ -21145,7 +21195,7 @@
   [(set (match_operand 0 "" "")
        (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
              (match_operand:DI 2 "" "")))]
-  "!SIBLING_CALL_P (insn) && TARGET_64BIT
+  "TARGET_64BIT && !SIBLING_CALL_P (insn)
    && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC"
 {
   if (constant_call_address_operand (operands[1], Pmode))
@@ -21158,7 +21208,7 @@
   [(set (match_operand 0 "" "")
        (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rm"))
              (match_operand:DI 2 "" "")))]
-  "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+  "TARGET_64BIT && !SIBLING_CALL_P (insn)"
   "call\t%A1"
   [(set_attr "type" "callv")])
 

diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 7ba7289922496149b787f078bd3c994487b77118..aac032d2c198d2a3d36c6f47532b45dd10a19436 100644 (file)
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -545,7 +545,9 @@
 ;; Test for a valid operand for a call instruction.
 (define_predicate "call_insn_operand"
   (ior (match_operand 0 "constant_call_address_operand")
-       (ior (match_operand 0 "register_no_elim_operand")
+       (ior (and (match_operand 0 "register_no_elim_operand")
+                (ior (match_test "TARGET_CALL_ESP")
+                     (match_operand 0 "index_register_operand")))
            (match_operand 0 "memory_operand"))))
 
 ;; Similarly, but for tail calls, in which we cannot allow memory references.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 130a5bcabffb838d4f9ac5493dd3419ffbf75366..3169cdec76ebc4e2e8990fcf9f65bf0a2e433632 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2009-11-05  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/41900
+       * gcc.target/i386/pr41900.c: New test.
+
 2009-11-04  Jason Merrill  <jason@redhat.com>
 
        PR c++/35067

diff --git a/gcc/testsuite/gcc.target/i386/pr41900.c b/gcc/testsuite/gcc.target/i386/pr41900.c
new file mode 100644 (file)
index 0000000..55f712d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr41900.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -fomit-frame-pointer -mpreferred-stack-boundary=2" } */
+
+int main ()
+{
+  volatile unsigned code = 0xc3;
+
+  ((void (*)(void)) &code) ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "call\[ \\t\]+\\*%esp" } } */