media: verisilicon: HEVC: Initialize start_bit field

The HEVC driver needs to set the start_bit field explicitly to avoid
causing corrupted frames when the VP9 decoder is used in parallel. The
reason for this problem is that the VP9 and the HEVC decoder share this
register.

Fixes: cb5dd5a0fa51 ("media: hantro: Introduce G2/HEVC decoder")
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Tested-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>

diff --git a/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c b/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
index 85a44143b3786b3a8afb3c634f428cb8c6e138b4..0e212198dd65b1cc27770ca93b14aa96e2772ac4 100644 (file)
--- a/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
+++ b/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
@@ -518,6 +518,7 @@ static void set_buffers(struct hantro_ctx *ctx)
        hantro_reg_write(vpu, &g2_stream_len, src_len);
        hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len);
        hantro_reg_write(vpu, &g2_strm_start_offset, 0);
+       hantro_reg_write(vpu, &g2_start_bit, 0);
        hantro_reg_write(vpu, &g2_write_mvs_e, 1);
 
        hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma);