PPC64, Add support for the Data Stream Control Register (DSCR)

diff --git a/NEWS b/NEWS
index 2dfcf32602f8501a287776a8712f5dc6e400cb4f..ca61811f0306a5de62325b0f18d8d84142474ded 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -58,6 +58,7 @@ where XXXXXX is the bug number as listed below.
 384526  reduce number of spill instructions generated by VEX register allocator v3
 384584  Callee saved registers listed first for AMD64, X86, and PPC architectures
 n-i-bz  Fix missing workq_ops operations (macOS)
+385182  PPC64 is missing support for the DSCR
 
 Release 3.13.0 (15 June 2017)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
index 8230d65b8afac762f9e04ac823623549f63ffddd..34adf62322d4a0e2598679441a8d9f9978da99d7 100644 (file)
--- a/VEX/priv/guest_ppc_helpers.c
+++ b/VEX/priv/guest_ppc_helpers.c
@@ -921,6 +921,7 @@ void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state )
    vex_state->guest_TEXASR = 0;
    vex_state->guest_PPR = 0x4ULL << 50;  // medium priority
    vex_state->guest_PSPB = 0x100;  // an arbitrary non-zero value to start with
+   vex_state->guest_DSCR = 0;
 }
 
 

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index a8d49263c62ded693e260a352aa7de1733961aab..2467f70f99657eb44a6c85bdd68ff1a4c2dcd5be 100644 (file)
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -296,6 +296,7 @@ static Bool OV32_CA32_supported = False;
 #define OFFB_TFIAR       offsetofPPCGuestState(guest_TFIAR)
 #define OFFB_PPR         offsetofPPCGuestState(guest_PPR)
 #define OFFB_PSPB        offsetofPPCGuestState(guest_PSPB)
+#define OFFB_DSCR        offsetofPPCGuestState(guest_DSCR)
 
 
 /*------------------------------------------------------------*/
@@ -459,6 +460,7 @@ typedef enum {
                       * automatically decrement. Could be added later if
                       * needed.
                       */
+    PPC_GST_DSCR,     // Data Stream Control Register
     PPC_GST_MAX
 } PPC_GST;
 
@@ -3068,6 +3070,9 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg )
    case PPC_GST_PSPB:
       return IRExpr_Get( OFFB_PSPB, ty );
 
+   case PPC_GST_DSCR:
+      return IRExpr_Get( OFFB_DSCR, ty );
+
    default:
       vex_printf("getGST(ppc): reg = %u", reg);
       vpanic("getGST(ppc)");
@@ -3344,6 +3349,11 @@ static void putGST ( PPC_GST reg, IRExpr* src )
                                           mkU64( 0x1C000000000000) ) ) );
       break;
       }
+   case PPC_GST_DSCR:
+      vassert( ty_src == Ity_I64 );
+      stmt( IRStmt_Put( OFFB_DSCR, src ) );
+      break;
+
    default:
       vex_printf("putGST(ppc): reg = %u", reg);
       vpanic("putGST(ppc)");
@@ -9407,6 +9417,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
          putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_XER ),
                                          /* Signed */False) );
          break;
+      case 0x3:  // 131
+         DIP("mfspr r%u (DSCR)\n", rD_addr);
+         putIReg( rD_addr, getGST( PPC_GST_DSCR) );
+         break;
       case 0x8:
          DIP("mflr r%u\n", rD_addr);
          putIReg( rD_addr, getGST( PPC_GST_LR ) ); 
@@ -9575,6 +9589,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
          DIP("mtxer r%u\n", rS_addr);
          putGST( PPC_GST_XER, mkNarrowTo32(ty, mkexpr(rS)) );
          break;
+      case 0x3:
+         DIP("mtspr r%u (DSCR)\n", rS_addr);
+         putGST( PPC_GST_DSCR, mkexpr(rS) );
+         break;
       case 0x8:
          DIP("mtlr r%u\n", rS_addr);
          putGST( PPC_GST_LR, mkexpr(rS) ); 

diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h
index 816ef5a3b4e27473cf24d4eb9291343a3559a7ab..bb48ac5bd2637e89125f6bc65b1e7bae3901524a 100644 (file)
--- a/VEX/pub/libvex_guest_ppc32.h
+++ b/VEX/pub/libvex_guest_ppc32.h
@@ -252,8 +252,8 @@ typedef
       /* 1388 */ ULong guest_PPR;       // Program Priority register
       /* 1396 */ UInt  guest_TEXASRU;   // Transaction EXception And Summary Register Upper
       /* 1400 */ UInt  guest_PSPB;      // Problem State Priority Boost register
+      /* 1404 */ ULong guest_DSCR;      // Data Stream Control register
       /* Padding to make it have an 16-aligned size */
-      /* 1404 */ UInt  padding2;
       /* 1408 */ UInt  padding3;
       /* 1412 */ UInt  padding4;
    }

diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h
index 02c4020ebf515c7fc52abd6593673aeddb0e338b..8c01fa64f9de6efd65c8d85ffa34981fe083951a 100644 (file)
--- a/VEX/pub/libvex_guest_ppc64.h
+++ b/VEX/pub/libvex_guest_ppc64.h
@@ -292,11 +292,12 @@ typedef
       /* 1686 */ ULong guest_PPR;       // Program Priority register
       /* 1694 */ UInt  guest_TEXASRU;   // Transaction EXception And Summary Register Upper
       /* 1698 */ UInt  guest_PSPB;      // Problem State Priority Boost register
+      /* 1702 */ ULong guest_DSCR;      // Data Stream Control register
 
       /* Padding to make it have an 16-aligned size */
-      /* 1698 */   UInt  padding1;
-   /* 1702    UInt  padding2; */
-   /* 1706    UInt  padding3; */
+      /* 1710 */   UInt  padding1;
+      /* 1714 */   UInt  padding2;
+      /* 1718 */   UInt  padding3;
 
    }
    VexGuestPPC64State;

diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
index 3ff7c446903c8c17f6a7e8fd406dfe468a4aeea9..1d57e0c3e00bda40671a27c2782de94e9cbfa498 100644 (file)
--- a/memcheck/mc_machine.c
+++ b/memcheck/mc_machine.c
@@ -194,6 +194,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
    if (o == GOF(TFIAR)     && sz == 8) return -1;
    if (o == GOF(PPR)       && sz == 8) return -1;
    if (o == GOF(PSPB)      && sz == 8) return -1;
+   if (o == GOF(DSCR)      && sz == 8) return -1;
 
    // With ISA 2.06, the "Vector-Scalar Floating-point" category
    // provides facilities to support vector and scalar binary floating-

diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
index a9a565bbc04bb124eadc73265d1e57f29c02523b..892e5035e92b5c2043d694c2286fa3cc868a0dea 100644 (file)
--- a/memcheck/mc_main.c
+++ b/memcheck/mc_main.c
@@ -4468,7 +4468,7 @@ static UInt mb_get_origin_for_guest_offset ( ThreadId tid,
 static void mc_post_reg_write ( CorePart part, ThreadId tid, 
                                 PtrdiffT offset, SizeT size)
 {
-#  define MAX_REG_WRITE_SIZE 1728
+#  define MAX_REG_WRITE_SIZE 1744
    UChar area[MAX_REG_WRITE_SIZE];
    tl_assert(size <= MAX_REG_WRITE_SIZE);
    VG_(memset)(area, V_BITS8_DEFINED, size);