ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 6367e09612bcd04056c079c35dbd79033d49a157..12de5c2d1717c82b7e0a57db535ae67e8ef65650 100644 (file)
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -46,6 +46,7 @@ _secure_monitor:
 #endif
 
        mcr     p15, 0, r1, c1, c1, 0           @ write SCR (with NS bit set)
+       isb
 
 #ifdef CONFIG_ARMV7_VIRT
        mrceq   p15, 0, r0, c12, c0, 1          @ get MVBAR value