LoongArch: Complete CPUCFG registers definition

According to the "LoongArch Reference Manual Volume 1: Basic
Architecture", begin with LA664 CPU core there are more features
supported which are indicated in CPUCFG2 and CPUCFG3. This patch
completes the definitions of them so as to match the architecture
specification.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index e6b8ff61c8cc6c23cbaf3b790e9a17b880374422..553c4dc7a156ef2606bcbf6e886b0384ec4e2353 100644 (file)
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -94,6 +94,12 @@
 #define  CPUCFG2_LSPW                  BIT(21)
 #define  CPUCFG2_LAM                   BIT(22)
 #define  CPUCFG2_PTW                   BIT(24)
+#define  CPUCFG2_FRECIPE               BIT(25)
+#define  CPUCFG2_DIV32                 BIT(26)
+#define  CPUCFG2_LAM_BH                        BIT(27)
+#define  CPUCFG2_LAMCAS                        BIT(28)
+#define  CPUCFG2_LLACQ_SCREL           BIT(29)
+#define  CPUCFG2_SCQ                   BIT(30)
 
 #define LOONGARCH_CPUCFG3              0x3
 #define  CPUCFG3_CCDMA                 BIT(0)
@@ -108,6 +114,7 @@
 #define  CPUCFG3_SPW_HG_HF             BIT(11)
 #define  CPUCFG3_RVA                   BIT(12)
 #define  CPUCFG3_RVAMAX                        GENMASK(16, 13)
+#define  CPUCFG3_DBAR_HINTS            BIT(17)
 #define  CPUCFG3_ALDORDER_CAP          BIT(18) /* All address load ordered, capability */
 #define  CPUCFG3_ASTORDER_CAP          BIT(19) /* All address store ordered, capability */
 #define  CPUCFG3_ALDORDER_STA          BIT(20) /* All address load ordered, status */