mips: mtmips: add CPU reset support for MT7628

Allow the system to reset the CPU without calling the reset
controller. This patch also removed the default SYSRESET controller
for MT7628, as it is now optional.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>

diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig
index 9c190cfc6ff391715b65a662d5d72f1f25d1b69e..a8c8be8ad43a599cc72a681083ee41776d6d06a4 100644 (file)
--- a/arch/mips/mach-mtmips/Kconfig
+++ b/arch/mips/mach-mtmips/Kconfig
@@ -104,8 +104,6 @@ config SOC_MT7628
        select PINCTRL_MT7628
        select PINCONF
        select MTK_SERIAL
-       select SYSRESET
-       select SYSRESET_RESETCTL
        select SPL_SEPARATE_BSS if SPL
        select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
        select SPL_LOADER_SUPPORT if SPL
@@ -113,7 +111,6 @@ config SOC_MT7628
        select SPL_SIMPLE_BUS if SPL_DM
        select SPL_DM_SERIAL if SPL_DM
        select SPL_CLK if SPL_DM && SPL_SERIAL
-       select SPL_SYSRESET if SPL_DM
        select SPL_OF_LIBFDT if SPL_OF_CONTROL
        help
          This supports MediaTek MT7628/MT7688.

diff --git a/arch/mips/mach-mtmips/mt7628/init.c b/arch/mips/mach-mtmips/mt7628/init.c
index 2996fd9ef4ee95a93bf2e88760d70eba6754fda1..a0e731121c9713f47dfc6b8056134f1893d75bad 100644 (file)
--- a/arch/mips/mach-mtmips/mt7628/init.c
+++ b/arch/mips/mach-mtmips/mt7628/init.c
@@ -110,3 +110,11 @@ ulong notrace get_tbclk(void)
 {
        return gd->arch.timer_freq;
 }
+
+void _machine_restart(void)
+{
+       void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
+
+       while (1)
+               writel(SYS_RST, sysc + SYSCTL_RSTCTL_REG);
+}

diff --git a/arch/mips/mach-mtmips/mt7628/mt7628.h b/arch/mips/mach-mtmips/mt7628/mt7628.h
index 391880b014e1062fe8d84030ad3910aeb1209afd..aac6e1278b255c87839c07966403323031ed6ac3 100644 (file)
--- a/arch/mips/mach-mtmips/mt7628/mt7628.h
+++ b/arch/mips/mach-mtmips/mt7628/mt7628.h
@@ -49,6 +49,7 @@
 
 #define SYSCTL_RSTCTL_REG              0x34
 #define MC_RST                         0x400
+#define SYS_RST                                0x01
 
 #define SYSCTL_AGPIO_CFG_REG           0x3c
 #define EPHY_GPIO_AIO_EN_S             17