drm/amdgpu/gfx12.1: Don't fetch default register values from hardware in mqd init

1. We can't assure the fetched values are always default register values.
   Observing non-zero cp_hqd_pq_rptr in mes_v12_1_self_test->init_mqd()
   where no GRBM_GFX_CNTL is specified.

2. See commit fc3c139cf043 ("drm/amdgpu/gfx12: don't read registers in mqd init").

Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 1da3da609f831a83a2898906ab369d0d39dbad18..1f567bd6cc4602d5f29c789d8b3d45d85ee22745 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -50,6 +50,14 @@
 
 #define RLCG_UCODE_LOADING_START_ADDRESS       0x00002000L
 
+#define regCP_HQD_EOP_CONTROL_DEFAULT                                             0x00000000
+#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT                                     0x00000000
+#define regCP_MQD_CONTROL_DEFAULT                                                 0x00000100
+#define regCP_HQD_PQ_CONTROL_DEFAULT                                              0x00308509
+#define regCP_HQD_PQ_RPTR_DEFAULT                                                 0x00000000
+#define regCP_HQD_PERSISTENT_STATE_DEFAULT                                        0x0ae06301
+#define regCP_HQD_IB_CONTROL_DEFAULT                                              0x00100000
+
 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc.bin");
 
@@ -2115,14 +2123,14 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m,
        mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 
        /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
-       tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HQD_EOP_CONTROL);
+       tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
        tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
                        (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1));
 
        mqd->cp_hqd_eop_control = tmp;
 
        /* enable doorbell? */
-       tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HQD_PQ_DOORBELL_CONTROL);
+       tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
 
        if (prop->use_doorbell) {
                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
@@ -2151,7 +2159,7 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m,
        mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
 
        /* set MQD vmid to 0 */
-       tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_MQD_CONTROL);
+       tmp = regCP_MQD_CONTROL_DEFAULT;
        tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
        mqd->cp_mqd_control = tmp;
 
@@ -2161,7 +2169,7 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m,
        mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 
        /* set up the HQD, this is similar to CP_RB0_CNTL */
-       tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HQD_PQ_CONTROL);
+       tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
                            (order_base_2(prop->queue_size / 4) - 1));
        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
@@ -2186,7 +2194,7 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m,
        tmp = 0;
        /* enable the doorbell if requested */
        if (prop->use_doorbell) {
-               tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HQD_PQ_DOORBELL_CONTROL);
+               tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
                tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
                                DOORBELL_OFFSET, prop->doorbell_index);
 
@@ -2201,17 +2209,17 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m,
        mqd->cp_hqd_pq_doorbell_control = tmp;
 
        /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
-       mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HQD_PQ_RPTR);
+       mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT;
 
        /* set the vmid for the queue */
        mqd->cp_hqd_vmid = 0;
 
-       tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HQD_PERSISTENT_STATE);
+       tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
        tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x63);
        mqd->cp_hqd_persistent_state = tmp;
 
        /* set MIN_IB_AVAIL_SIZE */
-       tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HQD_IB_CONTROL);
+       tmp = regCP_HQD_IB_CONTROL_DEFAULT;
        tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 1);
        mqd->cp_hqd_ib_control = tmp;